AMD claims Arm ISA doesn't offer efficiency advantage over x86
251–260 of 446 posts
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#252Earlier quoted context omitted.
Nice followup to your link: https://chipsandcheese.com/p/arm-or-x86-isa-doesnt-matter . Personally I do not entirely buy it. Intel and AMD have had plenty of years to catch up to Apple's M-architecture and they still aren't able to touch it in efficiency. The PC Snapdragon chips AFAIK also offer better performance-per-watt than AMD or Intel, with laptops offering them often having 10-30% longer battery life at simila…
I mean the M1 is nice but pretending that it can do in 110w what the 3090 does with 320w is Apple marketing nonsense. Like if your use case is playing games like cp2077, the 3090 will do 100fps in ultra ray tracing and an M4 Max will only do 30fps. Not to mention it’s trivial to undervolt nvidia cards and get 100% performance at 80% power. So 1/3 the power for 1/3 the performance? How is that smoking anything?
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#253This is an entirely uncontroversial take among experts in the space. x86 is an old CISC-y hot mess. RISC-V is a new-school hyper-academic hot mess. Recent ARM is actually pretty good. And none of it matters, because the uncore and the fabrication details (in particular, whether things have been tuned to run full speed demon or full power sipper) completely dominate the ISA. In the past x86 didn't dominate in low powe…
An annoying thing people have done since Apple Silicon is claim that its advantages were due to Arm. No, not really. The advantage is Apple prioritizing efficiency, something Intel never cared enough about.
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#254Earlier quoted context omitted.
"Transistors are free." That was pretty much the uArch/design mantra at intel.
Isn't that still true for high perf chips? We don't have ways to use all those transistors so we make larger and larger caches.
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#255Earlier quoted context omitted.
An annoying thing people have done since Apple Silicon is claim that its advantages were due to Arm. No, not really. The advantage is Apple prioritizing efficiency, something Intel never cared enough about.
Also Apple has a ton of cash that it can give to TSMC to essentially get exclusive access to the latest manufacturing process.
How have non-Apple chips on TSMC’s 5nm process compared with Apple’s M series?
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#256Earlier quoted context omitted.
I remember reading this Jim Keller interview: https://web.archive.org/web/20210622080634/https://www.anand... Basically the gist of it is that the difference between ARM/x86 mostly boils down to instruction decode, and: - Most instructions end up being simple load/store/conditional branch etc. on both architectures, where there's literally no difference in encoding efficiency - Variable length instruction has pretty…
x86 decoding must be a pain - I vaguely remember that they have trace caches (a cache of decoded micro-operations) to skip decoding in some cases. You probably don't make such caches when decoding is easy. Also, more complicated decoding and extra caches means longer pipeline, which means more price to pay when a branch is mispredicted (binary search is a festival of branch misprediction for example, and I got 3x acc…
They don't anymore they have uop caches, but trace caches are great and apple uses them [1].
They allow you to collapse taken branches into a single fetch.
Which is extreamly important, because the average instructions/taken-branch is about 10-15 [2]. With a 10 wide frontend, every second fetch would only be half utilized or worse.
> extra caches
This is one thing I don't understand, why not replace the L1I with the uop-cache entirely?
I quite like what Ventana does with the Veyron V2/V3. [3,4] They replaced the L1I with a macro-op trace cache, which can collapse taken branches, do basic instruction fusion and more advanced fusion for hot code paths.
[1] https://www.realworldtech.com/forum/?threadid=223220
[2] https://lists.riscv.org/g/tech-profiles/attachment/353/0/RIS... (page 10)
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#257Earlier quoted context omitted.
Indeed, the memory model has a decent impact. Unfortunately it's difficult to isolate in measurement. Only Apple has support for weak memory order and TSO in the same hardware.
Oh there’s an interesting idea. Given that Linux runs on the M1 and M2 Macs, would it be possible to do some kind of benchmark there where you could turn it on and off at will for your test program?
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#258Earlier quoted context omitted.
Eh, probably the biggest difference is in the OS. The amount of time Linux or Windows will spend using a processor while completely idle can be a bit offensive.
It’s all of the above. One thing Apple excels at is actually using their hardware and software together whereas the PC world has a long history of one of the companies like Intel, Microsoft, or the actual manufacturer trying to make things better but failing to get the others on-board. You can in 2025 find people who disable power management because they were burned (hopefully not literally) by some combination of ve…
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#259Earlier quoted context omitted.
> Why can't they decode 100 instructions per cycle? Well, obviously because there aren't 100 individual parallel execution units to which those instructions could be issued. And lower down the stack because a 3000 bit[1] wide cache would be extremely difficult to manage. An instruction fetch would be six (!) cache lines wide, causing clear latency and bottleneck problems (or conversely would demand your icache be 6x…
Wasn't the point of SMT that a single instruction decoder had difficulty keeping the core's existing execution units busy?
SMT is about addressing the underutilization of execution resources where your 6-wide superscalar processor gets 2.0 ILP.
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#260Earlier quoted context omitted.
I remember reading this Jim Keller interview: https://web.archive.org/web/20210622080634/https://www.anand... Basically the gist of it is that the difference between ARM/x86 mostly boils down to instruction decode, and: - Most instructions end up being simple load/store/conditional branch etc. on both architectures, where there's literally no difference in encoding efficiency - Variable length instruction has pretty…
Nice followup to your link: https://chipsandcheese.com/p/arm-or-x86-isa-doesnt-matter . Personally I do not entirely buy it. Intel and AMD have had plenty of years to catch up to Apple's M-architecture and they still aren't able to touch it in efficiency. The PC Snapdragon chips AFAIK also offer better performance-per-watt than AMD or Intel, with laptops offering them often having 10-30% longer battery life at simila…
Saying it offers a certain wattage worth of the desktop part means even less because it measures essentially nothing.
You would probably want to compare it to a mobile 3050 or 4050 although this still risks being a description of the different nodes more so than the actual parts.