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Intel completely disables AVX-512 on Alder Lake after all

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Re: Intel completely disables AVX-512 on Alder Lake after all

#251

Post by jiggawatts »

soheil wrote: post #241

"I hope AVX512 dies a painful death, and that Intel starts fixing real problems instead of trying to create magic instructions to then create benchmarks that they can look good on… I absolutely destest FP benchmarks, and I realize other people care deeply. I just think AVX512 is exactly the wrong thing to do. It’s a pet peeve of mine. It’s a prime example of something Intel has done wrong, partly by just increasing t…

Linus Torvald's opinion of AVX512 just doesn't matter.

It's like asking a 3D game programmer their opinion about FPGAs.

Re: Intel completely disables AVX-512 on Alder Lake after all

#252

Post by gnufx »

PragmaticPulp wrote: post #126
hajile wrote: post #118

Earlier quoted context omitted.

> The AVX-512 instructions not only weren’t enabled by default, they couldn’t be enabled at all unless you went out of your way to disable the efficiency cores completely. They also wouldn’t benefit your workload unless disabling those extra cores was offset by the AVX-512 instructions on the remaining cores. If your code benefits from AVX-512, it'll probably benefit from turning off the efficiency cores too. Sixteen…

> If your code benefits from AVX-512, it'll probably benefit from turning off the efficiency cores too. Maybe if you have a poorly parallelized problem where the bulk of the code is spent in AVX-512 instructions and you don’t ever do anything else on the computer, but that’s going to be rare for any consumer. > The real solution would be for Intel to detect the presence of AVX-512 instructions then automatically and…

I don't see how "poorly parallelized" is relevant compared with, say, a decent OpenMP BLAS which is likely to benefit from any reduced power consumption that allows a faster clock. In general on compute nodes it's worth turning off cores dynamically which aren't being used by jobs, like on a half-full node.

Re: Intel completely disables AVX-512 on Alder Lake after all

#253

Post by jeffbee »

dragontamer wrote: post #243
jeffbee wrote: post #240

Earlier quoted context omitted.

It's amazing how sticky the myth has become, though. On Ice Lake Xeon there is basically no penalty for using the AVX-512 unit.

It was true for several years, because Intel got "stuck" on Skylake due to issues in their manufacturing. If Intel was able to get Icelake out on time, it may have reduced the "stickiness" of the myth.

True. But the power penalty from 512 was already quite reduced in Cannon Lake (2018) and completely gone in Tiger Lake (2020).

Re: Intel completely disables AVX-512 on Alder Lake after all

#254

Post by gnufx »

formerly_proven wrote: post #73
codeflo wrote: post #11

If all of this was planned (and I’m not saying it is), that would have been very clever. It would work like this: 1. You “accidentally forget” to disable the feature in hardware. Given how competitive the market is, motherboard manufacturers can be relied upon to enable it in their “1337 OVERCLOCKZ” mode. No conspiracy is needed. 2. You “tolerate” this practice just long enough to win the critical initial wave of rev…

I've voiced this before but I think AVX-512 is completely irrelevant in the consumer space (which imho makes titles like "Intel artificially slows 12th gen down" incredulous). Even for commercial applications - sure there are some things that benefit from it. On the other hand, I work in HPC and even in (commercial, not nuke simulations or whatever the nuke powers do with their supercomputers) HPC applications AVX-51…

> HPC applications AVX-512 is rarely used

Your applications don't do linear algebra or FFT? AVX-512 is overrated for HPC generally, but it's surely going to be used by an optimized BLAS (unless there's only one FMA unit per core if the implementation is careful).

Compute nodes actually should have a big.little structure with a service core for the batch daemon etc.

Elsewhere, I see ~130 AVX512 instructions in this Debian system's libc.

Re: Intel completely disables AVX-512 on Alder Lake after all

#255

Post by smilekzs »

pantalaimon wrote: post #230
jeffbee wrote: post #201

Earlier quoted context omitted.

If you just want to play with AVX-512, you can rent an Ice Lake Xeon on AWS EC2 for only 3¢/hour, which strikes me as very hobby-friendly pricing.

But why would you want to play around with AVX512 if you can't benefit from it on your local machine?

e.g. to develop software that works well on servers that do support them?

Re: Intel completely disables AVX-512 on Alder Lake after all

#256

Post by gnufx »

kergonath wrote: post #220
formerly_proven wrote: post #73

Earlier quoted context omitted.

I've voiced this before but I think AVX-512 is completely irrelevant in the consumer space (which imho makes titles like "Intel artificially slows 12th gen down" incredulous). Even for commercial applications - sure there are some things that benefit from it. On the other hand, I work in HPC and even in (commercial, not nuke simulations or whatever the nuke powers do with their supercomputers) HPC applications AVX-51…

> On the other hand, I work in HPC and even in (commercial, not nuke simulations or whatever the nuke powers do with their supercomputers) HPC applications AVX-512 is rarely used. Even in the nuke simulations it is rarely used. More recent cores might be better, but the frequency drop and the associated latency kill performances on the clusters I know. And the new generation ones are AMD anyway.

As ever, it depends, probably on whether your code is dominated by matrix-matrix linear algebra. BLIS DGEMM on my SKX workstation runs at ~88GF, or ~48 if I restrict it to using the haswell configuration (somewhat different on a typical compute node).

But yes, I'd rather have twice the cores and memory bandwidth with AVX2. For those that don't know: non-benchmark code usually doesn't get close to peak floating point performance, constrained by memory bandwidth and/or inter-node communication. Everyone is trying to get the compute performance from GPUs anyway.

Re: Intel completely disables AVX-512 on Alder Lake after all

#257

Post by babypuncher »

formerly_proven wrote: post #73
codeflo wrote: post #11

If all of this was planned (and I’m not saying it is), that would have been very clever. It would work like this: 1. You “accidentally forget” to disable the feature in hardware. Given how competitive the market is, motherboard manufacturers can be relied upon to enable it in their “1337 OVERCLOCKZ” mode. No conspiracy is needed. 2. You “tolerate” this practice just long enough to win the critical initial wave of rev…

I've voiced this before but I think AVX-512 is completely irrelevant in the consumer space (which imho makes titles like "Intel artificially slows 12th gen down" incredulous). Even for commercial applications - sure there are some things that benefit from it. On the other hand, I work in HPC and even in (commercial, not nuke simulations or whatever the nuke powers do with their supercomputers) HPC applications AVX-51…

AVX-512 gives RPCS3 a pretty hefty boost, though that is arguably a niche consumer use case.

Re: Intel completely disables AVX-512 on Alder Lake after all

#258

Post by [deleted] »

SkeuomorphicBee wrote: post #10

Stuff like this is why I plan to never buy Intel ever again. I always disliked Intel's strategy for market segmentation by disabling specific instructions, I much prefer AMD's strategy of segmenting just by speed and number of cores. It is really annoying that with Intel you can't run the same program on the server and on your desktop, it makes development and testing a huge pain.

[deleted]

Re: Intel completely disables AVX-512 on Alder Lake after all

#259

Post by [deleted] »

codeflo wrote: post #11

If all of this was planned (and I’m not saying it is), that would have been very clever. It would work like this: 1. You “accidentally forget” to disable the feature in hardware. Given how competitive the market is, motherboard manufacturers can be relied upon to enable it in their “1337 OVERCLOCKZ” mode. No conspiracy is needed. 2. You “tolerate” this practice just long enough to win the critical initial wave of rev…

[deleted]

Re: Intel completely disables AVX-512 on Alder Lake after all

#260

Post by ChuckMcM »

This sort of thing is always a bad look for Intel, die costs are relatively fixed and "upselling" some of the transistors on the die for increased margins will always fail against a competitor who is willing to enable all the things (and AMD certainly seems to be in that camp). What it means is that AMD has an "easy" market strategy for continuing to beat Intel, just out feature them at a lower margin, turn Intel's fab capacity into an anchor rather than an asset.
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