Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

YC is wrong about LLMs for chip design

zach.be

Post reply on HN
Print view View original

241–250 of 283 posts

Re: YC is wrong about LLMs for chip design

#241

Post by truculent »

jamiequint wrote: post #112
sigh_again wrote: post #106

YC doesn't care whether it "makes sense" to use an LLM to design chips. They're as technically incompetent as any other VC, and their only interest is to pump out dogshit startups in the hopes it gets acquired. Gary Tan doesn't care about "making better chips": he cares about finding a sucker to buy out a shitty, hype-based company for a few billion. An old school investment bank would be perfect. YC is technically i…

First, VCs don't get paid when "dogshit startups" get acquired, they get paid when they have true outlier successes. It's the only way to reliably make money in the VC business. Second, want to give any examples of "shitty, hype-based compan[ies]" (I assume you mean companies with no real revenue traction) getting bought out for "a few billion". Third, investment banks facilitate sales of assets, they don't buy them…

> First, VCs don't get paid when "dogshit startups" get acquired

https://www.reuters.com/article/business/peloton-raises-12-b...

Re: YC is wrong about LLMs for chip design

#242

Post by adrian_b »

theptip wrote: post #138
zachbee wrote: post #120

Earlier quoted context omitted.

I didn't get into this in the article, but one of the major challenges with achieving superhuman performance on Verilog is the lack of high-quality training data. Most professional-quality Verilog is closed source, so LLMs are generally much worse at writing Verilog than, say, Python. And even still, LLMs are pretty bad at Python!

That’s what your VC investment would be buying; the model of “pay experts to create a private training set for fine tuning” is an obvious new business model that is probably under-appreciated. If that’s the biggest gap, then YC is correct that it’s a good area for a startup to tackle.

It would be hard to find any experts that could be paid "to create a private training set for fine tuning".

The reason is that those experts do not own the code that they have written.

The code is owned by big companies like NVIDIA, AMD, Intel, Samsung and so on.

It is unlikely that these companies would be willing to provide the code for training, except for some custom LLM to be used internally by them, in which case the amount of code that they could provide for training might not be very impressive.

Even a designer who works in those companies may have great difficulties to see significant quantities of archived Verilog/VHDL code, though it can be hoped that it still exists somewhere.

Re: YC is wrong about LLMs for chip design

#243

Post by yapyap »

but.. but.. muh AI

the AI hype train is basically investors not understanding tech, don’t get me wrong AI in itself could be a huge thing if used right but the things getting the most attention in the current market aren’t it

Re: YC is wrong about LLMs for chip design

#244

Post by adrian_b »

therealcamino wrote: post #184
cruffle_duffle wrote: post #135

Earlier quoted context omitted.

I kinda suspect that things that are expressed better with symbols and connections than with text will always be a poor fit to large LANGUAGE models. Turning what is basically a graph into a linear steam of text descriptions to tokenize and jam into an LLM has to be an incredibly inefficient and not very performant way of letting “AI” do magic on your circuits. Ever try to get ChatGPT to play scrabble? Ever try to de…

There are lots of reasons to doubt the present-day ability of LLMs to help with chip design, but I don't think any of these things above are why. Chip design isn't done with schematics. If an LLM can write Python given enough training data, it can write SystemVerilog given a similar amount of training (though the world currently lacks enough high-quality open source SV to reach an equivalent level.) We can debate whe…

The main problem in making a good circuit design, and actually also in writing a good program, is not writing per se.

The main problem is an optimal decomposition of the big project into a collection of interconnected modules and in defining adequate interfaces between modules.

This is not difficult when the purpose of the project is to just take an older project and make some improvements to it, when a suitable structure is already known, but it is always the main difficulty when a really new problem must be solved.

I have yet to see any example when a LLM can be used to help even in the slightest way to solve such an example of "divide et impera" for something novel, where novel by definition means that the training set has not contained the solution for an identical project.

There is pretty much no relationship between the 2-dimensional or multi-dimensional structural graph of the interconnected modules, together with the descriptions of their matching interfaces, and the proximity or frequency of tokens in the description of the circuit by a hardware design language. So there is little that a LLM could use to generate any HDL program for an unknown circuit.

What a LLM could do is only after a good designer has done the difficult job to decompose the project into modules and define the interfaces. When given a small module with its defined interfaces, a LLM might be able to find some boilerplate code to speed up the implementation of the module.

However, any good designer would already have templates for the boilerplate code and I can not really imagine how a LLM could do this faster than a designer who just selects the appropriate templates and pastes them into the module.

Re: YC is wrong about LLMs for chip design

#245

Post by snowwrestler »

brookst wrote: post #24
klabb3 wrote: post #10

I don’t mind LLMs in the ideation and learning phases, which aren’t reproducible anyway. But I still find it hard to believe engineers of all people are eager to put a slow, expensive, non-deterministic black box right at the core of extremely complex systems that need to be reliable, inspectable, understandable…

You find it hard to believe that non-deterministic black boxes at the core of complex systems are eager to put non-deterministic black boxes at the core of complex systems?

One great thing about humans is that we have developed ways to be deterministic when we want to. That’s what math is for.

Does an LLM know math? Not like we do. There’s no deductive logic in there; it’s all statistical inferences from language. An LLM doesn’t “work through” a circuit diagram systematically the way a physics student would. It observes the entire diagram at once, and then guesses the most likely next token.

Re: YC is wrong about LLMs for chip design

#246

Post by 1oooqooq »

sigh_again wrote: post #106

YC doesn't care whether it "makes sense" to use an LLM to design chips. They're as technically incompetent as any other VC, and their only interest is to pump out dogshit startups in the hopes it gets acquired. Gary Tan doesn't care about "making better chips": he cares about finding a sucker to buy out a shitty, hype-based company for a few billion. An old school investment bank would be perfect. YC is technically i…

not how i would word it, but yeah, any VC today is going to pump AI knowing it's the wrong tool, so the more complex they make the application space the easier it is to find the proverbial sucker.

Re: YC is wrong about LLMs for chip design

#247

Post by sph »

TheOtherHobbes wrote: post #206
sangnoir wrote: post #180

Earlier quoted context omitted.

> Why should we expect a general-purpose instruction-tuned LLM to get this right in the first place? The argument goes: Language encodes knowledge, so from the vast reams of training data, the model will have encoded the fundamentals of electromagnetism. This is based in the belief that LLMs being adept at manipulating language, are therefore inchoate general intelligences, and indeed, attaining AGI is a matter of sc…

Which is like saying that if you read enough textbooks you'll become an engineer/physicist/ballerina/whatever.

A huge number of people in academia believe so. The entire self-help literary genre is based upon this concept.

In reality, and with my biases as self-taught person, experience is crucial. Learning on the field. 10,000 hours of practice. Something LLMs are not very good at. You train them a priori, then it's a relatively static product compared to how human brains operate and self-adjust.

Re: YC is wrong about LLMs for chip design

#248

Post by lttlrck »

epolanski wrote: post #224
seattle_spring wrote: post #201

Earlier quoted context omitted.

I dropped EE entirely and switched from Computer Engineering to Computer Science because of my entry level EE course professor. I know I'm not the only person pushed away from EE due to Neil Cotter. Boggles my mind why he's still allowed to be the gateway to that discipline for so many people.

Most entry level engineering classes (first 3/4 semesters) in most of Europe (all kinds) are designed to gate keep. I graduated in chemistry, and Chemistry 1 in engineering had tests much more difficult than any other Chemistry 1 in any other faculty. After noticing that the same pattern applied to Physics 1 or Calculus I started realizing it was an engineering thing, which was later confirmed to me by an associate p…

Ahh perhaps that explains why I had Stress Analysis and Material Science in the first semester of CE... they were far harder than anything in following four years. I thought they were filler LOL. This was back in 92.

Re: YC is wrong about LLMs for chip design

#249

Post by staticman2 »

brookst wrote: post #24
klabb3 wrote: post #10

I don’t mind LLMs in the ideation and learning phases, which aren’t reproducible anyway. But I still find it hard to believe engineers of all people are eager to put a slow, expensive, non-deterministic black box right at the core of extremely complex systems that need to be reliable, inspectable, understandable…

You find it hard to believe that non-deterministic black boxes at the core of complex systems are eager to put non-deterministic black boxes at the core of complex systems?

>You find it hard to believe that non-deterministic black boxes at the core of complex systems are eager to put non-deterministic black boxes at the core of complex systems?

Hello, fellow tech enthusiasts, just stopping by to announce I performatively can't tell the difference between "Latest big tech product (TM)" and Homo Sapiens Sapiens!!!

I'll be seeing you in the next LLM related message thread with the same exact comment!!! As you were!!!

Re: YC is wrong about LLMs for chip design

#250

Post by famouswaffles »

kuhewa wrote: post #234
famouswaffles wrote: post #231

Earlier quoted context omitted.

If your task was being solved well by a deterministic script/algorithm, you are not going to save money porting to LLMs even if you use Open Source models.

'could' is doing a whole lot of work in that sentence, I'm being charitable. Reality is LLMs are being crammed in places where it isn't very sensible under thin justifications, just like the last few big ideas were (c.f. blockchain)

If it can't be solved by a script then what's problem with seeing if you can use LLMs ?

I guess I just don't see your point. So a few purported applications are not very sensible. So what ? This is every breakthrough ever.

Post reply on HN