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AMD claims Arm ISA doesn't offer efficiency advantage over x86

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Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#211
post #36

Since newer CPUs have heterogeneous cores (high performance + low power), I'm wondering if it makes sense to drop legacy instructions from the low power cores, since legacy code can still be run on the other cores. Then e.g. an OS compiled the right way can take advantage of extra efficiency without the CPU losing backwards compatibility

Like o11c says, that's setting everyone up for a bad time. If the heterogenous cores are similar, but don't all support all the instructions, it's too hard to use. You can build legacy instructions in a space optimized way though, but there's no reason not to do that for the high performance cores too --- if they're legacy instructions, one expects them not to run often and perf doesn't matter that much. Intel droppe…

Haven’t there been bugs found in older(?) games because of this?

They would run on the power core and detect the CPU features and turn on some AVX path.

Then the OS would reschedule them onto one of the efficiency courses and they would try and run the instructions that don’t exist there and it would crash?

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#212
post #88
post #79

Earlier quoted context omitted.

This is the flip side of Intel trying to drop AVX512 on their E cores in the 12th generation processors. It didn't work. It requires the OS to know which processes need AVX512 before they get run. And processes themselves use cpuid to determine the capability of processors and they don't expect it to change. So you basically must determine in advance which processes can be run on E cores and never migrate between cor…

What if the kernel handled unimplemented instruction faults by migrating the process to a core that does implement the instruction and restarting the faulting instruction?

What if that core isn’t free? What if it’s not going to be free for a long time?

That could be a recipe for random long stalls for some processes.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#213
post #19

Earlier quoted context omitted.

We've seen CPU-capability differences by accident a few times, and it's always a chaotic mess leading to SIGILL. The kernel would need to have a scheduler that knows it can't use those cores for certain tasks. Think about how hard you would have to work to even identify such a task ...

Current windows or linux executable format don't even list the used instruction though. And even it is listed, how about dynamic linkables? The program may decide to load library at any time it wishes, and the OS is not going to know what instruction may be used this time.

You couldn’t even scan the executable if you wanted to. Because lots of code will check what the CPU is capable of doing and choose the most efficient path based on what instructions it’s allowed to use.

So until you’ve run it (halting problem) you may find instructions that you’d never even run.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#214
Interesting to see this show up literally the day after I post a comment with this 11-year-old article on the same topic:

https://www.extremetech.com/extreme/188396-the-final-isa-sho...

It is a little ironic to see AMD making the backwards-compatibility argument, when they were the ones who made the very inelegant AMD64, had some known differences to Intel's CPUs in some edge-cases, and then much later, https://www.os2museum.com/wp/vme-broken-on-amd-ryzen/

There are some very-low-power x86 SoCs which are largely found in embedded systems; the most famous of these may be https://en.wikipedia.org/wiki/Vortex86

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#215
post #117

I'm glad an authoritative source has stated this. It's been ongoing BS for years. I first got into ARM machines with the Acorn Archimedes and even back then, people were spouting some kind of intrinsic efficiency benefit to ARM that just didn't make any sense.

It is true for small cores, it's just not important for big cores compared to all the other things you have to solve.

Makes sense. A 386 had 275,000 transistors. You can see how instruction decode stuff for a more complex x86 instruction could be a reasonable fraction of that.

ArrowLake is 17.8 billion. Even if you divide by the core count instruction decode obviously isn’t much of that.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#216

The ISA is the contract or boundary between software and hardware. While there is a hardware cost to decode instructions, the question is how much? As all the fanbois in the thread have have pointed out, Apple's M series is fast and efficient compared to x86 for desktop/server workloads. What no one seems to acknowledge is that Apple's A series is also fast and efficient compared to other ARM implementations in mobil…

Whatever the hardware cost is it must pale in comparison to trying to implement the instructions set directly. Wasn’t that the huge benefit of the Pentium Pro?

The main reason to have both A and M series chips, I think, is related to which custom processors are available as well as how many of each. There’s no point in putting the full GPU from an M4 into a cell phone, it’s just gonna waste a ton of power.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#217

Earlier quoted context omitted.

By PMIC, did you mean VRM ?, if not, can you tell me the difference between them ?

I'm not an expert on the topic and don't really know the difference. But in the video they say it can finetune power delivery to individual parts of the SoC and reduce idle power.

Well, Every single CPU need some kind of voltage regulation module to work.

About "fine tune" part, this does not relate to PMIC(or VRM) at all, more like CPU design: How many power domain does this CPU have ?

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#218

This is an entirely uncontroversial take among experts in the space. x86 is an old CISC-y hot mess. RISC-V is a new-school hyper-academic hot mess. Recent ARM is actually pretty good. And none of it matters, because the uncore and the fabrication details (in particular, whether things have been tuned to run full speed demon or full power sipper) completely dominate the ISA. In the past x86 didn't dominate in low powe…

An annoying thing people have done since Apple Silicon is claim that its advantages were due to Arm. No, not really. The advantage is Apple prioritizing efficiency, something Intel never cared enough about.

Apple also buys out basically all of TSMC's initial capacity for their leading edge node so generally every time a new Apple Silicon thing comes out it's a process node ahead of every other chip they're comparing to.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#219

I was just window-shopping laptops this morning, and realized ARM-based doesn't necessarily hold battery life advantages.

Plus they are not cheap either.

I Blame that on Qualcomm. Right now they are the only vendor with ARM CPU on Windows. And using QC CPU means you must buy their whole "solution".

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#220

Earlier quoted context omitted.

How much of the Mac's impressive battery life is due purely to CPU efficiency, and how much is due to great vertical integration and the OS being tuned for power efficiency? It's a genuine question; I'm sure both factors make a difference but I don't know their relative importance.

The overwhelming majority is due to the power management software, yes. Other ARM laptops do not get anywhere close to the same battery life. The MNT Reform with 8x 18650s (24000mAh, 3x what you get an MBP) gets about 5h of battery life with light usage.

The MNT Reform does not use Li-Ion batteries, resulting in much poorer energy density. It's going to depend on the cells being used but this is what I could see from the Reform Next detail page: 8× LiFePO4 cells (16000 mAh total). Assuming 2200mah cells, I think this nets you around 56 Wh in a 4S2P configuration, Li-Ion cells would be closer to 65 Wh.

According to Apple's website it seems a 14 inch macbook pro has a 70 Wh battery.

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