201–210 of 415 posts
Earlier quoted context omitted.
I love the probabilistic nature of this. Presentations could be anywhere from extremely impressive to hilariously embarrassing.
It would be so cool if it generated live in the presentation and adjusted live as you spoke, so you’d have to react to whatever popped on screen!
Earlier quoted context omitted.
Bigger chip = more surface area = higher chance for somewhere in the chip to have a manufacturing defect Yields on silicon are great, but not perfect
Does that mean smaller chips are made from smaller wafers?
really too bad that the codex models are so tightly coupled to the codex harness as to be useless for everything else edit: not useless in a absolute sense, but worse than the vanilla gpt models
Earlier quoted context omitted.
I love the probabilistic nature of this. Presentations could be anywhere from extremely impressive to hilariously embarrassing.
It would be so cool if it generated live in the presentation and adjusted live as you spoke, so you’d have to react to whatever popped on screen!
Earlier quoted context omitted.
> What am I missing? Largest production capacity maybe? Also, market demand will be so high that every player's chips will be sold out.
> Largest production capacity maybe? Anyone can buy TSMC's output...
Earlier quoted context omitted.
Nope. They use the same size wafers and then just put more chips on a wafer.
So, does a wafer with a huge chip has more defects per area than a wafer with 100s of small chips?
The WSE-3 is the largest AI chip ever built, measuring 46,255 mm² and containing 4 trillion transistors. It delivers 125 petaflops of AI compute through 900,000 AI-optimized cores — 19× more transistors and 28× more compute than the NVIDIA B200.
From https://www.cerebras.ai/chip:
https://cdn.sanity.io/images/e4qjo92p/production/78c94c67be9...
https://cdn.sanity.io/images/e4qjo92p/production/f552d23b565...
