It's not the ISA. Modern Macbooks are power-efficient because they have: - RAM on package - PMIC power delivery - Better power management by OS Geekerwan investigated this a while ago, see: https://www.youtube.com/watch?v=Z0tNtMwYrGA https://www.youtube.com/watch?v=b3FTtvPcc2s https://www.youtube.com/watch?v=ymoiWv9BF7Q Intel and AMD have implemented these improvements with Lunar Lake and Strix Halo. You can buy an x…
AMD claims Arm ISA doesn't offer efficiency advantage over x86
201–210 of 446 posts
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#202Earlier quoted context omitted.
I remember reading this Jim Keller interview: https://web.archive.org/web/20210622080634/https://www.anand... Basically the gist of it is that the difference between ARM/x86 mostly boils down to instruction decode, and: - Most instructions end up being simple load/store/conditional branch etc. on both architectures, where there's literally no difference in encoding efficiency - Variable length instruction has pretty…
Apple’s ARM cores have wider decode than x86 M1 - 8 wide M4 - 10 wide Zen 4 - 4 wide Zen 5 - 8 wide
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#203After playing around with some ARM hardware I have to say that I don't care whether ARM is more efficient or not as long as the boot process remains the clusterfuck that it is today. IMHO the major win of the IBM PC platform is that it standardized the boot process from the very beginning, first with the BIOS and later with UEFI, so you can grab any random ISO for any random OS and it will work. Meanwhile in the ARM…
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#204Earlier quoted context omitted.
> I have to assume that amd and intel would like similar chips They historically haven't. They've wanted the higher single-core performance and frequency and they've pulled out all the stops to get it. Everything had been optimized for this. (Also, they underinvested in their uncores, the nastiest part of a modern processor. Part of the reason AMD is beating Intel right now despite being overall very similar is their…
Not arguing, but I would think there is (and always has been) very wide demand for fastest single core perf. From all the usual suspects? Thank you.
I suspect one of the issues is that pushing the clock is a really easy way to get an extra 2% so you can claim the crown of fastest or try to win benchmarks. It’s easy to fall into a trap of continuing to do that over and over.
But we know the long-term result. You end up blasting out a ton of heat and taking up a ton of power, even though you may only be 10% faster than a competitor who did things differently. Or worse you try to optimize for ever increasing clocks and get stuck like the Pentium 4.
As said up thread, no one really compares Apple CPU speeds with megahertz. That’s partially because Apple doesn’t talk about it or emphasize it which makes it more difficult, and partially because it’s not like you have a choice anyway.
It would never happen but it would be interesting to see how things would develop if it was possible to simply ban talking about clock speeds somehow. What would that do to the market?
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#205Earlier quoted context omitted.
What's it due to? At least this, probably more. - more advanced silicon architecture. Apple spends billions to get access to the latest generation a couple of years before AMD. - world class team, with ~25 years of experience building high speed low power chips. (Apple bought PA Semi to make these chips, which was originally the team that build the DEC StrongARM). And then paid & treated them properly, unlike Intel &…
How many of those engineers remain, didn't a lot go to Nuvia that was then bought by Qualcomm?
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#206Earlier quoted context omitted.
What choices? The main thing that comes to mind is lack of exceptions on integer overflow but you are unlikely meaning this.
- Handling of misaligned loads/stores: RISC-V got itself into a weird middle ground, ops on misaligned pointers may work fine, may work "extremely slow", or cause fatal exceptions (yes, I know about Zicclsm, it's extremely new and only helps with the latter, also see https://github.com/llvm/llvm-project/issues/110454 ). Other platforms either guarantee "reasonable" performance for such operations, or forbid misaligne…
Not a RISC-V programmer, but this drives me crazy on ARM. Dozens of optional features, but the FEAT_ bits are all readable only from EL1, and it's unspecified what API the OS exposes to query it and which feature bits are exposed. I don't care if it'd be slow, just give us the equivalent of a dedicated CPUID instruction, even if it just a reserved opcode that traps to kernel mode and is handled in software.
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#207It's not the ISA. Modern Macbooks are power-efficient because they have: - RAM on package - PMIC power delivery - Better power management by OS Geekerwan investigated this a while ago, see: https://www.youtube.com/watch?v=Z0tNtMwYrGA https://www.youtube.com/watch?v=b3FTtvPcc2s https://www.youtube.com/watch?v=ymoiWv9BF7Q Intel and AMD have implemented these improvements with Lunar Lake and Strix Halo. You can buy an x…
By PMIC, did you mean VRM ?, if not, can you tell me the difference between them ?
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#208Earlier quoted context omitted.
> Why can't they decode 100 instructions per cycle? Well, obviously because there aren't 100 individual parallel execution units to which those instructions could be issued. And lower down the stack because a 3000 bit[1] wide cache would be extremely difficult to manage. An instruction fetch would be six (!) cache lines wide, causing clear latency and bottleneck problems (or conversely would demand your icache be 6x…
Wasn't the point of SMT that a single instruction decoder had difficulty keeping the core's existing execution units busy?
But I could be way off…
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#209Earlier quoted context omitted.
What's it due to? At least this, probably more. - more advanced silicon architecture. Apple spends billions to get access to the latest generation a couple of years before AMD. - world class team, with ~25 years of experience building high speed low power chips. (Apple bought PA Semi to make these chips, which was originally the team that build the DEC StrongARM). And then paid & treated them properly, unlike Intel &…
interesting, ty re: apple getting exclusive access to the best fab stuff: https://appleinsider.com/articles/23/08/07/apple-has-sweethe... . Interesting.
I think Apple helps them with money (loan?) to get some of the equipment or build the new lines. In exchange they get first shot at buying capacity.
And of course Apple is certainly paying for the privilege of the best process. At least more than other companies are willing. And they must buy a pretty tremendous volume across a couple of sizes.
It benefits both companies, otherwise they wouldn’t do it.
Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86
#210Earlier quoted context omitted.
> That's not mostly because of a better ISA Genuinely asking -- what is it due to? Because like the person you're replying to, the m* processors are simply better: desktop-class perf on battery that hangs with chips with 250 watt TDP. I have to assume that amd and intel would like similar chips, so why don't they have them if not due to the instruction set? And AMD is using TSMC, so that can't be the difference.
> Genuinely asking -- what is it due to? Mostly memory/cache subsystem. Apple was willing to spend a lot of transistors on cache because they were optimizing the chips purely for mobile and can bury the extra cost in their expensive end products. You will note that after the initial wins from putting stonking amounts of cache and memory bandwidth in place, Apple has not had any significant performance jump beyond the…
The M2 was certainly nothing amazing in jump.