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YC is wrong about LLMs for chip design

zach.be

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Re: YC is wrong about LLMs for chip design

#201

Post by seattle_spring »

hinkley wrote: post #105
spamizbad wrote: post #21

LLMs have a long way to go in the world of EDA. A few months ago I saw a post on LinkedIn where someone fed the leading LLMs a counter-intuitively drawn circuit with 3 capacitors in parallel and asked what the total capacitance was. Not a single one got it correct - not only did they say the caps were in series (they were not) it even got the series capacitance calculations wrong. I couldn’t believe they whiffed it a…

I still have nightmares about the entry level EE class I was required to take for a CS degree. RC circuits man.

I dropped EE entirely and switched from Computer Engineering to Computer Science because of my entry level EE course professor. I know I'm not the only person pushed away from EE due to Neil Cotter. Boggles my mind why he's still allowed to be the gateway to that discipline for so many people.

Re: YC is wrong about LLMs for chip design

#202

Post by nuancebydefault »

zachglabman wrote: post #197

LLMs are wrong for most things imo. LLMs are great conversational assistants, but there is very little linguistic rigor to them, if any. They have almost no generalization ability, and anecdotally they fall for the same syntactic pitfalls they've fallen for since BERT. Models have gotten so good at predicting this n-dimensional "function" that sounds like human speech, we're getting distracted from seeing their actua…

The 2 first paragraphs are in contradiction with my results with working with LLMs. There is definitely some form of reasoning that has emerged. Some people will still find it not convincing enough to be called reasoning, but that just a quantitative limitation at the moment.

With respect to AGI in its broadest sense: indeed it is not in reach. I think that is for the better!

Re: YC is wrong about LLMs for chip design

#203

Post by blincoln »

kuhewa wrote: post #130
famouswaffles wrote: post #94

Earlier quoted context omitted.

>If I can choose between having a script that queries the db and generates a report and “Dave in marketing” who “has done it for years” If you could that would be nice wouldn't it? And if you couldn't? If people were saying, "let's replace Casio Calculators with interfaces to GPT" then that would be crazy and I would wholly agree with you but by and large, the processes people are scrambling to place LLMs in are ones…

> by and large, the processes people are scrambling to place LLMs in are ones that typical machines struggle or fail I'm pretty sure they are scrambling to put them absolutely anywhere it might save or make a buck (or convince an investor that it could)

100%, and a lot of them are truly terrible use cases for LLMs.

For example, using a LLM to transform structured data into JSON, and doing it with two LLMs in parallel to try to catch the inevitable failures, instead of just writing code that outputs JSON.

Re: YC is wrong about LLMs for chip design

#204

Post by shash »

lizknope wrote: post #171

I've been designing chips for almost 30 years. We have a bunch of AI initiatives in my company but most of them are about using Copilot to help write scripts to automate the design flow. Our physical design flow are thousands of lines of Tcl and Python code. The article mentions High Level Synthesis. I've been reading about this since my first job in the 1990's. I've worked on at least 80 chips and I've never seen an…

I've never tried SystemC. But after having tried to learn Chisel and friends, and successfully learning Bluespec (and using it in professional projects), I have some insights.

It's fundamentally important when doing hardware design to work in a language that _expresses_ itself like you're designing hardware. Verilog (for all its faults) shines there because it feels like you're writing a slightly higher level netlist. That's not the case with SC and friends, which doesn't allow you to think in hardware. Languages like BSV and SV are functionally similar but they force you to think in similar ways to Verilog, meaning you can write much tighter high-level code.

I'd be interested in your experience, but I feel that using normal programming languages to build hardware is an abstraction failure. Which is why it performs so poorly.

Re: YC is wrong about LLMs for chip design

#205

Post by shash »

therealcamino wrote: post #185
grepLeigh wrote: post #30

Nvidia is trying something similar: https://blogs.nvidia.com/blog/llm-semiconductors-chip-nemo/ I'd want to know about the results of these experiments before casting judgement either way. Generative modeling has actual applications in the 3D printing/mechanical industry.

That sounds like good work, but we can't ignore the context. Nvidia can train their own LLM's on proprietary Nvidia designs, which isn't a possibility for a random startup. If the evaluation of the approach is "it works great if you train it on a few decades of the best designs from a successful fabless semiconductor company", I would say that if you plan to use that method as a startup, you're clearly going to fail.…

The problem _there_ is that there's very little diversity in the training data - it's all NVidia designs which are probably from the same phylogenetic tree. It'll probably end up regurgitating existing NV designs...

Re: YC is wrong about LLMs for chip design

#206

Post by TheOtherHobbes »

sangnoir wrote: post #180
nerdponx wrote: post #174

Earlier quoted context omitted.

> I couldn’t believe they whiffed it Why should we expect a general-purpose instruction-tuned LLM to get this right in the first place? I am not at all surprised it didn't work, and I would be more than a little surprised if it did.

> Why should we expect a general-purpose instruction-tuned LLM to get this right in the first place? The argument goes: Language encodes knowledge, so from the vast reams of training data, the model will have encoded the fundamentals of electromagnetism. This is based in the belief that LLMs being adept at manipulating language, are therefore inchoate general intelligences, and indeed, attaining AGI is a matter of sc…

Which is like saying that if you read enough textbooks you'll become an engineer/physicist/ballerina/whatever.

Re: YC is wrong about LLMs for chip design

#207

Post by herval »

namaria wrote: post #166
herval wrote: post #161

Earlier quoted context omitted.

it seems that's sufficient to do a lot of things better than the average human - including coding, writing, creating poetry, summarizing and explaining things...

A human specialized in any of those things vastly outperforms the average human let alone an LLM.

You’re entirely missing the point

Re: YC is wrong about LLMs for chip design

#208

Post by mafuyu »

seattle_spring wrote: post #201
hinkley wrote: post #105

Earlier quoted context omitted.

I still have nightmares about the entry level EE class I was required to take for a CS degree. RC circuits man.

I dropped EE entirely and switched from Computer Engineering to Computer Science because of my entry level EE course professor. I know I'm not the only person pushed away from EE due to Neil Cotter. Boggles my mind why he's still allowed to be the gateway to that discipline for so many people.

While I didn’t switch majors, I had a similar experience with my intro EE class. My theory was that it was intentionally a weeder class to push students towards the other engineering concentrations.

Intro EE is kinda brutal in that there’s a lot of theory to cover, and you need to build the intuition on how it applies to real world circuit design on the fly.

I had a bit of an epiphany when I was in a set theory/number theory class and some classmates were breezing through proofs that I struggled with. I was having to do algebraic manipulations in a way that was novel to me, but was intuitive to math nerds. I felt like that guy who didn’t “get” the intuition in an intro programming or circuits class.

But yeah, students often get some context for math or programming in high school, but rarely for circuit design. E&M in physics at best. EE programs have solved this by weeding out anyone who can’t bash their way through the foundational theory… which isn’t great.

If you’re still interested, I would recommend the Student Manual to the Art of Electronics. It’s a very practical, lab-based book that throws out a lot of the math in favor of rules of thumb and gaining intuition for circuit design.

Re: YC is wrong about LLMs for chip design

#209

Post by garyfirestorm »

sangnoir wrote: post #180
nerdponx wrote: post #174

Earlier quoted context omitted.

> I couldn’t believe they whiffed it Why should we expect a general-purpose instruction-tuned LLM to get this right in the first place? I am not at all surprised it didn't work, and I would be more than a little surprised if it did.

> Why should we expect a general-purpose instruction-tuned LLM to get this right in the first place? The argument goes: Language encodes knowledge, so from the vast reams of training data, the model will have encoded the fundamentals of electromagnetism. This is based in the belief that LLMs being adept at manipulating language, are therefore inchoate general intelligences, and indeed, attaining AGI is a matter of sc…

This could be up for debate -

https://www.scientificamerican.com/article/you-dont-need-wor...

Re: YC is wrong about LLMs for chip design

#210

Post by zh2408 »

klabb3 wrote: post #10

I don’t mind LLMs in the ideation and learning phases, which aren’t reproducible anyway. But I still find it hard to believe engineers of all people are eager to put a slow, expensive, non-deterministic black box right at the core of extremely complex systems that need to be reliable, inspectable, understandable…

Human itself is like a slow, expensive, non-deterministic black box...
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