Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching • Hacker News Board

Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching

#21

Post by domipheus » Fri, Jul 24, 2015, 8:10 AM UTC

gluggymug wrote: post #9

domipheus wrote: post #5

Earlier quoted context omitted.

Hey - author here. I'm not wanting to learn industry practices, it's a hobby project. May look into things like that later, though. The other article parts have the disclaimer that says I have no idea what I'm doing ;) Cheers for the feedback :)

Uh oh. I didn't realize you were actually on HN. Apologies if my other spiel seems too harsh. Perhaps the better sounding term would be "engineering practices" rather than "industry practices". If it's a hobby, you still want to get a good result out of your effort. That principle in industry still applies to the hobbyist IMO. The signal names issue that alain94040 mentioned was just an example of one problem with th…

Hah, don't worry - I didn't think it was harsh. I've had no training/edu in HDL whatsoever, so this was a deep dive - I expected to be told I'm doing wrong!

The end result is on FPGA, yes. Still a long way before that works. And I'll make sure any massive screwups are documented in next parts, those are the best parts (and, probably most valuable) to write about :)

Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching

#22

Post by domipheus » Fri, Jul 24, 2015, 8:16 AM UTC

gluggymug wrote: post #6

alain94040 wrote: post #3

Not a great codebase, if you are trying to learn the industry's best practices. For instance, I recommend naming your RTL signals based on which pipeline stage they belong to. Assuming this thing even has a pipeline.

Not a great codebase. That's putting it lightly. It does have a pipeline BTW. Industry is so different I don't know where to start complaining. Xilinx tools are not used for simulation usually because they suck and we generally pay those other tool vendors for their stuff so we might as well use them. Given that newbies don't want to pay, maybe Xilinx is the best. I don't know much about the free stuff. Looking at pr…

This is some great stuff, thanks for all the feedback - seriously. My VHDL experience is probably about 2/3 online tutorials, and they were all behavioural. The main aim of the articles are for me to learn.

The point about documentation is valid. However, as I've has no training at all in this, I'd be writing a document that basically has no value. After this project has come to it's conclusion, I'll probably go try again using processes/methods learned.

Thanks again for the feedback :)

Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching

#23

Post by gluggymug » Fri, Jul 24, 2015, 1:06 PM UTC

domipheus wrote: post #22

gluggymug wrote: post #6

Earlier quoted context omitted.

Not a great codebase. That's putting it lightly. It does have a pipeline BTW. Industry is so different I don't know where to start complaining. Xilinx tools are not used for simulation usually because they suck and we generally pay those other tool vendors for their stuff so we might as well use them. Given that newbies don't want to pay, maybe Xilinx is the best. I don't know much about the free stuff. Looking at pr…

This is some great stuff, thanks for all the feedback - seriously. My VHDL experience is probably about 2/3 online tutorials, and they were all behavioural. The main aim of the articles are for me to learn. The point about documentation is valid. However, as I've has no training at all in this, I'd be writing a document that basically has no value. After this project has come to it's conclusion, I'll probably go try…

Learning by doing is cool.

You don't have to do it the conventional way.

It's just that from my perspective, I can only focus on the future problems. I am too traumatized from the HW experience! I almost rewrote a couple of my points again just now.:)

You are documenting via your blog in a sense. It has value. It is a high level representation of your plans for the project.

Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching

#24

Post by alain94040 » Fri, Jul 24, 2015, 2:10 PM UTC

nhaehnle wrote: post #10

alain94040 wrote: post #3

Not a great codebase, if you are trying to learn the industry's best practices. For instance, I recommend naming your RTL signals based on which pipeline stage they belong to. Assuming this thing even has a pipeline.

So, where is a great codebase for somebody who wants to learn?

I keep pointing people to the page I started a while back: Verilog for Software programmers (https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for...)

Maybe it's time for me to add another one: good Verilog RTL coding style, or basic RTL rules for Verilog... Based on the kinds of mistakes I see online, it would be easy to cover initial blocks, multiple assignments, etc.

EDIT: just started https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_RTL... . For now, just contains placeholders for the items I want to cover, but feel free to add to the list, that's the whole point of a wiki.