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Why Intel is adding instructions to speed up non-volatile memory

danluu.com

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Re: Why Intel is adding instructions to speed up non-volatile memory

#21

Post by soamv »

Animats wrote: post #5

Computing really hasn't figured out how to handle non-volatile memory as yet. It's almost always used to emulate rotating disks, with file systems, named files, and a trip through the OS to access anything. Access times for non-volatile memory are orders of magnitude faster than disk access times, so small accesses are feasible. But that's not how it's treated under existing operating systems. There are alternatives.…

Well, this is about userspace access to nvram, with the nvram mapped as memory. It just so happens that cache management is one of the hard parts of doing that, so that's what these new instructions are for.

Re: Why Intel is adding instructions to speed up non-volatile memory

#24

Post by signa11 »

0x0 wrote: post #23

Isn't there a higher risk of data loss, if your "hard drive" is 100% memory mapped - all it would take is one buggy kernel driver writing to an invalid pointer or memset'ing the whole thing to 0?

well, the same is true now as well right ? for example, a buggy driver can override a buffer-cache pointer with something else, and then you are hosed. if you are playing in the kernel-land and not careful enough, you are courting disaster...

Re: Why Intel is adding instructions to speed up non-volatile memory

#25

Post by the8472 »

fleitz wrote: post #16
bahahah wrote: post #12

There are several storage class memories that are nearing commercialization. Intel is betting big on at least one of them. Most technologies in this class are orders of magnitude faster and have orders of magnitude better endurance than flash memory, while being only slightly slower the DRAM, yet non-volatile. It is plausible that with another layer of in-package cache they could eliminate DRAM altogether, replacing…

Is this basically memristors coming to market or are memristors still a few years off?

This should be useful for any type of NVRAM, be it battery-backed DRAM, MRAM, memristors or DMA-mapped flash.

Re: Why Intel is adding instructions to speed up non-volatile memory

#26

Post by JoeAltmaier »

0x0 wrote: post #23

Isn't there a higher risk of data loss, if your "hard drive" is 100% memory mapped - all it would take is one buggy kernel driver writing to an invalid pointer or memset'ing the whole thing to 0?

Certainly damage can happen faster, since the NVRAM is faster. But my buggy driver could write the whole disk to 0 already.

Re: Why Intel is adding instructions to speed up non-volatile memory

#27

Post by JoeAltmaier »

shaurz wrote: post #22

How to solve the context switch overhead issue: https://www.destroyallsoftware.com/talks/the-birth-and-death...

How about: a cpu that has scores of hyperthreads? They don't block in the kernel; they stall on a semaphore register bitmask. That mask can include timer register matches another register; interrupt complete; event signaled.

Now I can do almost all of my I/o, timer and inter-process synchronization without ever entering a kernel or swapping out thread context. I've been waiting for this chip since the Z80.

Re: Why Intel is adding instructions to speed up non-volatile memory

#28

Post by runeks »

bahahah wrote: post #12

There are several storage class memories that are nearing commercialization. Intel is betting big on at least one of them. Most technologies in this class are orders of magnitude faster and have orders of magnitude better endurance than flash memory, while being only slightly slower the DRAM, yet non-volatile. It is plausible that with another layer of in-package cache they could eliminate DRAM altogether, replacing…

> There are several storage class memories that are nearing commercialization.

I'm very interested in this. Could you point out which technologies that are near ready for commercialization?

My understanding is that the current cost is orders of magnitude higher per unit of storage for these new technologies compared to NAND flash or even DDR3 RAM. But of course, a dedicated fab could change that very quickly.

Re: Why Intel is adding instructions to speed up non-volatile memory

#30

Post by 6cxs2hd6 »

abhaybhuva wrote: post #29

Full coverage is here: http://www.improgrammer.net/intel-adding-instructions-speed-...

I'm downvoting your comment because

- that seems to be copy and pasted (i.e. plagiarized) from the original blog post http://danluu.com/clwb-pcommit/

- your submission history suggests you are associated with improgrammer.net

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