This is a quite nice article and an interesting project. Related: A coworker of mine wrote a 3d accelerator with FPGA that outperforms some of the early Voodoo -era 3d accelerators. It could do higher triangle counts at a higher resolution with multisample antialiasing. The demos he had looked quite spectacular. He is a software engineer and he gave us a very nice demo and a very enlightening presentation on how writ…
Would you be able to share platform/performance numbers? I've actually been thinking about doing something like this but I'm coming from the opposite direction (hardware guy who's always wanted to learn more about 3D graphics).
Output was bit-banged VGA signal into a cheap-ass monitor.
Like the first Voodoo-era 3d accelerators, it was a triangle rasterizer with Z-buffering and perspective correct texture mapping. Ie. there was no 3d transformations done on the chip, they were done on the CPU. The limiting factor in the demos was actually the ARM CPU (synthetic on the FPGA) which couldn't push enough triangles to keep the GPU busy.
It was a tile based rasterizer (in two stages: coarse and fine) rather than a scanline rasterizer (like SW rasterizers in the Quake era).
This is pretty much all I can remember about it.