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The adder at the heart of Intel's 8087 floating-point chip

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Re: The adder at the heart of Intel's 8087 floating-point chip

#21

Post by kens »

throwaway152321 wrote: post #6

Do you have any insights on how power was delivered to these circuits? Maybe it's done in the metal layers that were dissolved? Also, is it correct that there is no on die capacitance surrounding these circuits? Thanks for the great article.

The 8087 has one metal layer, which makes power distribution more challenging. You want to keep power distribution in the metal, so for the most part the pattern is two interdigitated trees for power and ground. There are a few places where the lines need to cross, which is accomplished with a short polysilicon connection underneath. The two clock lines are also kept in metal whenever possible.

The die photo at the start of the article shows some of the power distribution (the thick white lines around the edge and through the die). I have a close-up shot of the adder's metal layer in the article, showing the thick power and ground metal lines that run next to the adder.

As far as capacitors, there are some capacitors for specific things, but no decoupling capacitors. I think the capacitors are mostly to tweak the timing, if a signal needs to be delayed slightly.

Re: The adder at the heart of Intel's 8087 floating-point chip

#22

Post by rcxdude »

Aardwolf wrote: post #5
kens wrote: post #2

Author here for your 8087 questions. I find adders and ALUs interesting because they are key to the performance of a system and every system implements them differently.

Any idea how much adder designs changed on modern CPUs compared to back then? I mean there's only so much you can optimize in those, I think...

There's a surprising amount of optimization possible in them. You can improve the latency of them substantially at the cost of a lot more transistors.

Re: The adder at the heart of Intel's 8087 floating-point chip

#23

Post by userbinator »

JdeBP wrote: post #10

It is interesting that over the years people have produced synthesizable RTL HDL for the 8086/8088 and later, with varying degrees of fidelity, but no-one seems to have produced similar for the 8087.

A lot of applications where an embedded x86 core makes sense don't have a huge need for FP maths.

Re: The adder at the heart of Intel's 8087 floating-point chip

#24

Post by Sharlin »

inigyou wrote: post #13
ErroneousBosh wrote: post #9

Earlier quoted context omitted.

I knew a guy who bred snakes but could never really get much out of his adders. Turns out what he needed to do was saw up some tree trunks to make rough platforms for them, and they bred like crazy. Adders can multiply really efficiently with log tables.

slow clap

(It's an old, old joke.)

Re: The adder at the heart of Intel's 8087 floating-point chip

#26

Post by B1FF_PSUVM »

rcxdude wrote: post #22
Aardwolf wrote: post #5

Earlier quoted context omitted.

Any idea how much adder designs changed on modern CPUs compared to back then? I mean there's only so much you can optimize in those, I think...

There's a surprising amount of optimization possible in them. You can improve the latency of them substantially at the cost of a lot more transistors.

For example, an adder's total delay depends on a carry chain. If you have N 4-bit slices, the last slice has to wait for the carry to propagate through all N-1 previous slices.

But if you duplicate all your slices, you can have the results for both carry = 0 and carry = 1 inputs. Then just switch which one is correct - total time 1 add plus N-1 switches.

Just for double (and change) the hardware. Cheap.

Re: The adder at the heart of Intel's 8087 floating-point chip

#27

Post by B1FF_PSUVM »

kens wrote: post #16
Aardwolf wrote: post #5

Earlier quoted context omitted.

Any idea how much adder designs changed on modern CPUs compared to back then? I mean there's only so much you can optimize in those, I think...

Even by the time of the Pentium, they had moved to much more complicated adders like Kogge-Stone. I wrote about it here: https://www.righto.com/2025/01/pentium-carry-lookahead-rever...

Do you have anything on those TRW floating point chips that used to titillate junior engineers in trade mag advertisements before that?

Re: The adder at the heart of Intel's 8087 floating-point chip

#29

Post by bsder »

Aardwolf wrote: post #5
kens wrote: post #2

Author here for your 8087 questions. I find adders and ALUs interesting because they are key to the performance of a system and every system implements them differently.

Any idea how much adder designs changed on modern CPUs compared to back then? I mean there's only so much you can optimize in those, I think...

I believe that every single adder architecture we now use was known by 1980s. The "optimization" is matching the theory to the engineering of the day.

The reason you don't use prefix adders in 1980 is that you can't possibly route them because you don't have enough metal. So instead, you use chunks of Manchester carry chain because the "tapping internal nodes" that everybody cites allows you to route nodes in diffusion and polysilicon instead of having to use metal.

Of course, THAT only works because you have 5V (or more) and can connect lots of transistors in series and still have them work. As your voltage falls you can't connect as many transistors in series, so you switch to architectures that prefer active gates over passthroughs and long chains.

So, as your available metal layers, supply voltage, transistor speed, threshold voltages, capacitive load and power dissipation all shift over the engineering landscape, your "optimization" shifts with it.

Re: The adder at the heart of Intel's 8087 floating-point chip

#30

Post by librasteve »

great post … thanks for all the work

personally I would like to see a compare and contrast between the Intel 8087 (built around an full width adder), 287 and the Weitek 1167 (built around a full width mac and barrel shifter)

as you note, all these parts were pushing the transistor limits of their day

PS. and the Inmos T800 had a log shifter … so a compromise between those extremes

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