My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
Oftentimes slow is fine, when the work is parallel and the hardware is cheap
which, sadly, isnt the case right now
The RISE RISC-V Runners: free, native RISC-V CI on GitHub
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Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#22Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#23Earlier quoted context omitted.
Oftentimes slow is fine, when the work is parallel and the hardware is cheap
which, sadly, isnt the case right now
It is the case for embedded microcontrollers. An ESP32-C series is about as cheap as you can get a WiFi controller, and it includes one or more RISC-V cores that can run custom software. The Raspberry Pi Pico and Milk-V Duo are both a few dollars and include both ARM and RISC-V view. with all but the cheapest Duo able to run Linux.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#24My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
Same experience here.
At least for SBCs, I’ve bought a few orange pi rv2s and r2s to use as builder nodes, and in some cases they are slower than the same thing running in qemu w/buildx or just qemu
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#25My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
Some of that could be related to the ISA but I'm hoping that it's just the fact that the current implementations aren't mature enough.
The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#26My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
Some of that could be related to the ISA but I'm hoping that it's just the fact that the current implementations aren't mature enough. The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
The RISC-V ISA can be fast.
Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years.
The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation).
This should give you an idea about how fast RISC-V is improving.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#27My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
Oftentimes slow is fine, when the work is parallel and the hardware is cheap
RISC-V microcontrollers are inexpensive but “application” processors will be expensive until volumes increase.
Performance will get “good enough” over the next 2 years. Prices will drop after that.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#28Earlier quoted context omitted.
Oftentimes slow is fine, when the work is parallel and the hardware is cheap
RISC-V microcontrollers are inexpensive but “application” processors will be expensive until volumes increase. Performance will get “good enough” over the next 2 years. Prices will drop after that.
That the "good enough" SoCs will be arriving "over the next 2 years" is what the RISC-V advocates have told us for quite a few years now.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#29My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
That has been the case so far but is changing this year. The SpacemiT K3 is faster than QEMU. Much faster chips are expected to release over the next few months. I mean things like the Milk-V Pioneer were already faster but expensive. One thing that has been frustrating about RISC-V is that many companies close to releasing decent chips have been bought and then those chips never appear (Ventana, Rivos, etc). That an…
One thing I observed is that RVV code is usually slower in QEMU
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#30My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
The arrival of the first RVA23 chips, which is expected next month, will change the status quo.
Besides RVA23 compliance, these are dramatically faster than earlier chips, enough for most people's everyday computing needs i.e. web browsing, video decoding and such. K3 got close to rpi5 per-core performance, but with more cores, better peripherals, and 32GB RAM possible, although unfortunately current RAM prices are no good.
And it'll only get better from there, as other, much faster, RVA23 chips like Tenstorrent Alastor ship later this year.