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DDR4 Sdram – Initialization, Training and Calibration

systemverilog.io

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Re: DDR4 Sdram – Initialization, Training and Calibration

#21

Post by nsteel »

bri3d wrote: post #19
nsteel wrote: post #16

Implementing DDR3 training for our packet queuing chip (custom memory controller) was my first project at work. We had originally hoped to use the same training params for all parts. That wasn't reliable even over a small number of testing systems in the chamber. DDR3 RAM parts were super cheap compared to what we had used in previous generations, and you get what you pay for with a huge amount of device variation. S…

You played in hard mode in a weird sense; more modern DDR versions are in a backwards sense "easier" if you're buying the IP, because a lot of the training has moved to boot time and is handled by the vendor IP rather than needing to be run during burn-in using some proprietary toolkit or self-test tool. It's just as arcane and weird, but if you buy one of the popular modern packages for DDR4/5 like DesignWare, more…

I don't know if this is still the case, but back then the likes of Synopsys charged a lot of money for what was very limited controller functionality; you were stuck with their frustrating support channels and generally dumpster fire firmware. Our controller was fully custom to our needs, supporting more optimum refresh schemes tightly integrated with our application, and multiple memory protocols (not just DDR3), and I don't remember what else.

At least we were able to modify the training algorithms and find the improvements, rather than being stuck with the usual vendor "works for us" response. Especially with something like commodity DDR, where our quantities don't command much clout. But it was a bit of an ordeal and may have contributed to us buying in a controller for our next gen (not DDRx). But I think we're going the other way again after that experience..!

Re: DDR4 Sdram – Initialization, Training and Calibration

#22

Post by p_l »

nopurpose wrote: post #13
MisterTea wrote: post #2

From my understanding, memory training is/was a closely held secret of memory makers and EDA IP houses who sold memory controller IP to all the chip vendors. This in turn makes fully open motherboard firmware almost impossible as no one can write code for memory training to bring up the chip. That piece of code has to be loaded as a blob - if you can get the blob.

I remember listening to Oxide & Friends (or it was On the Metal?) podcast few years ago and had an impression they wrote their own training code.

It's a more available option on AMD chips, intel AFAIK kept it a secret blob.

Ultimately oxide got to run customised firmware deal and AFAIK even got custom PSP firmware

Re: DDR4 Sdram – Initialization, Training and Calibration

#23

Post by v1ne »

Does anybody else's fingers also tingle like this is written by an AI?

The formatting is strangely inconsistent, highlighting only some numbers and some variables in fixed-width font. Also there's odd statements like that the reference resistor keeps its value "at all temperatures", which is just not true. Other phrases like "poly-silicon resistor" are highlighted, and then not explained. All in all, I find this article to be quite a mess and not a clear explanation.

Re: DDR4 Sdram – Initialization, Training and Calibration

#24

Post by kvemkon »

bri3d wrote: post #20
Aurornis wrote: post #11

Earlier quoted context omitted.

I think you're mixing different concepts. JEDEC doesn't define DDR4 training procedures so there isn't a secret that's being withheld. Everyone who implements a DDR4 controller has to develop and implement a training procedure to meet the specifications. On a DDR4 motherboard the training would occur between the memory controller and the DDR4 RAM. The proprietary blob you need would include the communication with the…

What you're saying is true, but the OP has a point too. What's basically happening is that as things get faster the lifetime of training data decreases because the system becomes more sensitive to environmental conditions, so training procedures which were previously performed earlier in the manufacturing cycle are now delegated to the runtime, so the system migrates from data to code. Previously, you or the vendor w…

> environmental conditions

Shouldn't it be: no more negligible manufacturing / assembly tolerances instead? I mean, when I turn PC on, the temperature of all components is 20 C, the training is done at almost this temperature. But then the PC can work for months with much more higher memory controller and DRAM chips temperatures.

Re: DDR4 Sdram – Initialization, Training and Calibration

#25

Post by halifaxbeard »

bri3d wrote: post #19
nsteel wrote: post #16

Implementing DDR3 training for our packet queuing chip (custom memory controller) was my first project at work. We had originally hoped to use the same training params for all parts. That wasn't reliable even over a small number of testing systems in the chamber. DDR3 RAM parts were super cheap compared to what we had used in previous generations, and you get what you pay for with a huge amount of device variation. S…

You played in hard mode in a weird sense; more modern DDR versions are in a backwards sense "easier" if you're buying the IP, because a lot of the training has moved to boot time and is handled by the vendor IP rather than needing to be run during burn-in using some proprietary toolkit or self-test tool. It's just as arcane and weird, but if you buy one of the popular modern packages for DDR4/5 like DesignWare, more…

Wow, I was spoiled building firmware for my ARM boards then (building, not developing).

Marvell has a source available DDR driver that actually takes care of training on a few of their platforms! https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell

Re: DDR4 Sdram – Initialization, Training and Calibration

#26

Post by Neywiny »

namibj wrote: post #17
Neywiny wrote: post #14

Earlier quoted context omitted.

You need to train whether you're on one die or 100. It's about your per bit skew and PVT

Yes, I was just pointing out why we choose to make the memory chips so fragile/dependant on the controller doing all the magic training for them.

Well no, your comment answered that we need training because the dies are made cheaply. But no amount of money would prevent the need to train out static and dynamic delays. If it wasn't in the controller it'd be in the memory and the question of why it's needed would still be relevant.

Re: DDR4 Sdram – Initialization, Training and Calibration

#27

Post by Aurornis »

bri3d wrote: post #20
Aurornis wrote: post #11

Earlier quoted context omitted.

I think you're mixing different concepts. JEDEC doesn't define DDR4 training procedures so there isn't a secret that's being withheld. Everyone who implements a DDR4 controller has to develop and implement a training procedure to meet the specifications. On a DDR4 motherboard the training would occur between the memory controller and the DDR4 RAM. The proprietary blob you need would include the communication with the…

What you're saying is true, but the OP has a point too. What's basically happening is that as things get faster the lifetime of training data decreases because the system becomes more sensitive to environmental conditions, so training procedures which were previously performed earlier in the manufacturing cycle are now delegated to the runtime, so the system migrates from data to code. Previously, you or the vendor w…

The parent commenter was mixing two concepts together.

DDR4 training is not defined. It’s vendor-implemented.

If you want to work with a vendor’s memory controller chip, you need the documentation for that chip.

So the secret isn’t memory training (the topic of this article) it’s just proprietary chips on motherboards. Memory training is only one of many things that have to be reverse engineered or known for an open firmware.

Re: DDR4 Sdram – Initialization, Training and Calibration

#28

Post by MertsA »

v1ne wrote: post #23

Does anybody else's fingers also tingle like this is written by an AI? The formatting is strangely inconsistent, highlighting only some numbers and some variables in fixed-width font. Also there's odd statements like that the reference resistor keeps its value "at all temperatures", which is just not true. Other phrases like "poly-silicon resistor" are highlighted, and then not explained. All in all, I find this arti…

There are some typos like "if" instead of "of" that seem to imply at the very least, some of it is verbatim written by a person. Given the subject matter, I'd be extremely surprised if this was 100% AI but one thing I've totally done for similar technical writing is ask AI for help refining a rough draft. There's some suggestions I'd ignore but the larger grammatical and sentence structure suggestions I'd usually adopt.
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