21–30 of 53 posts
some of my favorite projects from tiny tapeout: https://tinytapeout.com/chips/tt05/tt_um_rejunity_sn76489 https://tinytapeout.com/chips/tt07/tt_um_rejunity_ay8913 https://tinytapeout.com/chips/tt04/tt_um_morningjava_top
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Yes, actually 180 nm still represents a sizable amount of the market, in terms of volume! In more niche applications where chips contain lots of analog functionlity, you can still find plenty of designs being done in 180, 130, 110, and 65 nm. Most corporate designs don't disclose this, but I'd venture to guess the majority of integrated circuits in your home are made on these larger "process nodes". I work in 65nm an…
Thanks for offering. Do you do analog design, and which market niche are you targeting: low cost per part or something else?
We can save money during initial prototyping, by creating a small test structure as small as 1mmm^2, which reduces the cost of a prototype run to 5k$ - 10k$. Some services that provide this are MOSIS [0] in the US, and Europractice [1] in the EU. But when we go to a full production run, there's no way to get around creating a 'full reticle' design, as image sensors have a physical dimension determined by focal plan size requirement of imaging application. For example, in digital camera, if a sensor is 'full frame' then it obviously has to be 36mm x 24mm, regardless of if the process node would have let you shrink it. And if you make a serious mistake, then you need to do another production run, which means you pay the 300k$ - 1m$ once again.
In terms of the circuit functionality, image sensors require a mixture of analog and digital design, but in this area, even many of the digital circuits are custom designed, rather than relying on foundry-provided 'standard cells' and an automatic place-and-route flow.
Earlier quoted context omitted.
Yes, actually 180 nm still represents a sizable amount of the market, in terms of volume! In more niche applications where chips contain lots of analog functionlity, you can still find plenty of designs being done in 180, 130, 110, and 65 nm. Most corporate designs don't disclose this, but I'd venture to guess the majority of integrated circuits in your home are made on these larger "process nodes". I work in 65nm an…
I'm not OP, but perhaps you, or somebody else here, could answer my question, albeit one that is slightly off-topic. In the recent years, in part courtesy of cryptoindustry investment, there were many advancements in zero-knowledge mathematics and applied cryptography. I've been on-and-off researching computational approaches to liquid democracy[1], on the off-chance that we may one day apply it in my country, Ukrain…
From the 2025 Free Silicon Conference:
https://wiki.f-si.org/index.php?title=The_Transparent_Refere...
https://wiki.f-si.org/images/e/eb/OpenFab%40FSiC2025.pdf
The initiative started in Germany, where the research institute IHP already provides an open source 130nm PDK and associated foundry, but interest is spreading. Here's the abstract from that talk:
"The European Chips Act aims to double Europe’s share in global semiconductor manufacturing to 20% by 2030. However, most current investments focus on leading-edge nodes and pilot lines, which – while important – are not sufficient to achieve broad capacity scaling. At the same time, demand for mature nodes (≥65 nm) remains strong: over two-thirds of chips in automotive and industrial sectors still rely on nodes ≥90 nm, and this trend is expected to persist through 2030. This contribution introduces the concept of a Transparent Reference Fab – a fully open, scalable semiconductor fabrication model designed to serve as a blueprint for sovereign and trustworthy chip manufacturing in Europe. Unlike traditional pilot lines, the Transparent Reference Fab is production-ready and replicable. It includes open access to process design kits (PDKs), equipment configurations, process recipes, and operational know-how. The fab targets mature nodes, especially 65 nm CMOS, and is intended to be built on existing infrastructure to reduce time-to-market and technical risk. We argue that such a model can significantly multiply Europe’s production capacity by enabling private and public actors to replicate the reference fab across regions. This approach would not only strengthen Europe’s position in strategic semiconductor supply chains but also foster innovation, education, and security through transparency. The paper presents the strategic rationale, technical architecture, and implementation path, positioning the Transparent Reference Fab as a critical instrument for European resilience and competitiveness."
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I didn't even know that 180nm was still a thing but clearly it is because apparently the cost difference is like USD 100M for 180nm vs USD 10B or more for the latest tech? Is it true that we will likely have these 180nm chips for things like light bulbs for the foreseeable future?
Yes, actually 180 nm still represents a sizable amount of the market, in terms of volume! In more niche applications where chips contain lots of analog functionlity, you can still find plenty of designs being done in 180, 130, 110, and 65 nm. Most corporate designs don't disclose this, but I'd venture to guess the majority of integrated circuits in your home are made on these larger "process nodes". I work in 65nm an…
It doesn't benefit from 22nm - analog blocks generally don't scale down at all, they have to be a particular size to achieve particular current handling, inductance etc. requirements. But we need the production line availability.
The thing I love about blog posts like these is how it reminds me that the tech world is a vast ocean that encompasses so many disciplines; it's not all full stack web development. Related: I did not understand 95% of what she wrote.
- IC design software (at a startup bought by Cadence)
- an IC (contract out of Dallas semi)
- FPGA HFT acceleration
- fixing some OS drivers for Windows CE
- finding a compiler bug
- various bits of embedded firmware in C and assembly for various platforms
- debugging with a scope
- desktop applications
- a web server (defunct ZWS)
- web apps (Perl. Long time ago)
Somehow I've never written a react app.
Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes.
Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software.
When you combine it with a fixed shuttle date like in the article it is even worse because if you miss that date it might be another 1-2 months for the next shuttle instead of just a day for day slip when you control all the masks.
I've probably worked on 70 chips over the last 30 years. Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes. Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software. When you combine it with a fixed shuttle date like in the article it is even worse because if…
I don’t work much on apps anymore but I hear it’s somewhat better now.
Another big area is compliance, those processes can take forever.
I've probably worked on 70 chips over the last 30 years. Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes. Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software. When you combine it with a fixed shuttle date like in the article it is even worse because if…
Earlier quoted context omitted.
This project exists, here it is: https://opentitan.org/
I previously came across OpenTitan, but it's hardware design only, right? It doesn't actually concern itself with bringing up transparent manufacturing process? For example, I couldn't find anything about the costs necessary to bring up a fab?