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PlayStation 3 Architecture (2021)

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Re: PlayStation 3 Architecture (2021)

#21

Post by xgkickt »

rtpg wrote: post #18

I remember hearing somebody talk about programming hot loops in either the the PS3 or PS2 in Excel, to get a good handle on the concurrency question by having assembler in multiple columns next to each other

That would be the PS2’s VUs which had an upper and lower pipe and it was easier to write instructions for each in separate columns. Then in one SDK we received program called vcl which took a single list of instructions, doing all the pipelining for you, as well as optimizing loops and assigning registers automatically. It was a godsend.

Re: PlayStation 3 Architecture (2021)

#22

Post by flipacholas »

rideontime wrote: post #11
flipacholas wrote: post #7

Earlier quoted context omitted.

Please see this: https://github.com/flipacholas/Architecture-of-consoles > A suggestion from me is to provide sources, and also maybe an epub of this What do you mean?

It seems they missed this. https://payhip.com/copetti

That was a small fundraiser started to convert all articles into epubs, finished in 2022

Re: PlayStation 3 Architecture (2021)

#23

Post by lepicz »

i did a bit dev on ps3 and i remember there was a small memory on the chip, like 256k that was accessible to programmer.

i always found this very appealing, having a blazing fast memory under programmer control so i wonder: why don't we have that on other cpus?

Re: PlayStation 3 Architecture (2021)

#24

Post by bitwize »

lepicz wrote: post #23

i did a bit dev on ps3 and i remember there was a small memory on the chip, like 256k that was accessible to programmer. i always found this very appealing, having a blazing fast memory under programmer control so i wonder: why don't we have that on other cpus?

The TI-99/4A had 256 BYTES (128 words) of static RAM available to the CPU. All accesses the 16K of main memory had to be done through the video chip. This made a lot of things on the TI-99/4A slow, but there were occasional bits of brilliance where you see a tiny bit of the system it could've been. Thanks to the fast SRAM and 16-bit CPU, the smooth scrolling in Parsec was done entirely in software—the TMS9918A video chip lacking scroll registers entirely.

Re: PlayStation 3 Architecture (2021)

#25

Post by mabster »

xgkickt wrote: post #21
rtpg wrote: post #18

I remember hearing somebody talk about programming hot loops in either the the PS3 or PS2 in Excel, to get a good handle on the concurrency question by having assembler in multiple columns next to each other

That would be the PS2’s VUs which had an upper and lower pipe and it was easier to write instructions for each in separate columns. Then in one SDK we received program called vcl which took a single list of instructions, doing all the pipelining for you, as well as optimizing loops and assigning registers automatically. It was a godsend.

I can't remember the details because we coded the SPU in C, but the PS3 SPUs had odd and even cycles with different access properties too.

Re: PlayStation 3 Architecture (2021)

#26

Post by jl6 »

I remember discussion at the time about how the PS3 was a uniquely difficult architecture to emulate. Was that true? Have those difficulties now been overcome? I see RPCS3 exists but I’ve no idea if it has done the difficult parts.

Re: PlayStation 3 Architecture (2021)

#27

Post by nikanj »

jl6 wrote: post #26

I remember discussion at the time about how the PS3 was a uniquely difficult architecture to emulate. Was that true? Have those difficulties now been overcome? I see RPCS3 exists but I’ve no idea if it has done the difficult parts.

With sufficient thrust, pigs fly just fine. Eventually you can overcome any issues by throwing more CPU at the problem

Re: PlayStation 3 Architecture (2021)

#28

Post by moomoo11 »

nickpsecurity wrote: post #20
rtpg wrote: post #18

I remember hearing somebody talk about programming hot loops in either the the PS3 or PS2 in Excel, to get a good handle on the concurrency question by having assembler in multiple columns next to each other

Sounds like a Gantt chart with code might fit.

I love those

Re: PlayStation 3 Architecture (2021)

#29

Post by flohofwoe »

lepicz wrote: post #23

i did a bit dev on ps3 and i remember there was a small memory on the chip, like 256k that was accessible to programmer. i always found this very appealing, having a blazing fast memory under programmer control so i wonder: why don't we have that on other cpus?

> why don't we have that on other cpus

Pure speculation from my side, but I'd think that the advantages over traditional big register banks and on-chip caches are not that great, especially when you're writing 'cache-aware code'. You also need to consider that the PS3 was full of design compromises to keep cost down, e.g. there simply might not have been enough die space for a cache controller for each SPU, or the die space was more vaulable to get a few more kilobytes of static scratch memory instead of the cache logic.

Also, AFAIK on some GPU architectures you have something similar like per-core static scratch space, that's where restrictions are coming from that uniform data per shader invocation may at most be 64 KBytes on some GPU architectures, etc...

Re: PlayStation 3 Architecture (2021)

#30

Post by frankbell »

nxobject wrote: post #3
amelius wrote: post #2

Can it run deep learning workloads?

The PS3 was used a few time in clusters – some NN work was done on it back in the day. My understanding (somewhat echoed in TFA) is that when programming Cell, you really needed to think about communication patterns to avoid quickly running into memory bandwidth limitations, especially given memory hierarchy and bus quirks. https://open.clemson.edu/all_theses/629/

See also QPACE https://en.wikipedia.org/wiki/QPACE
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