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Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

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Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#21

Post by st_goliath »

Ygg2 wrote: post #20
st_goliath wrote: post #8

Earlier quoted context omitted.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

> and no, a 50 line comment block with a German transcription of the code below is not documentation You had it good back then. Now it's a one-line comment in Chinese. Line is 300 characters wide. /Yorkshire men skit.

Now that's funny. The irony here is that, besides German (native), I do speak some HSK4-ish Mandarin as a 3rd language. A few years ago, a single line Chinese comment next to a blob of magic hex values did help me figure out a bug in a touch controller driver :-)

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#22

Post by imtringued »

adwn wrote: post #6

I don't understand the table under Benchmark Results . To compare the quality of two toolchains, the device architecture needs to be the same. "LUT6" vs "LUT4" doesn't cut it, there's much, much more to the architecture of an FPGA than the width of its look-up tables [1], and even for the "LUT6" category, I see four different devices. [1] Consequently, there's more to FPGA synthesis than LUT mapping, so take the repo…

Not just that, their device "z1060" doesn't exist outside this blog post. We literally don't know what it is.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#23

Post by robinsonb5 »

adwn wrote: post #18
aappleby wrote: post #15

Earlier quoted context omitted.

"there's no publicly available documentation of the signal routing configuration or the bitstream format" Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

> Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered. Please provide a source for this claim. Yosys, for example, can't route [1] designs even for Xilinx 7-series devices, and that architecture has been introduced 15 years ago. [1] Not to be confused with synthesis , mapping , or placing , all of which come earlier in the flow, and for all of which sufficient…

Yosys doesn't do place-and-route - typically that part would be handled by nextpnr, and there's an experimental fork of that for Xilinx series 7 devices: https://github.com/openXC7/ (full toolchain)

It works well enough to build a working litex RISC-V SOC capable of running Linux, for the QMTech Kintex-7 325T board.

I don't think the Cyclone V project has got as far, but I could be wrong. (It kind of slipped off my radar after I realised I was spending way too much time on Discord and purged all but a very few servers to reduce my distractions.)

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#24

Post by elsjaako »

rowanG077 wrote: post #19

This is not a separate synthesis tool. This is just a yosys plugin and only works for their own FPGAs. Kind of leaves a bad taste in my mount that they choose to advertise this as their own synthesis tool when it isn't. I'm curious why they didn't work together with upstream. Also looking to their full stack it seem they use VPR/VTR instead of nextpnr for routing. That seems like a backwards choice.

When you release something as open source, a third party grabbing it and releasing it is explicitly something that can be done.

I can't speak for them, so I'm not sure, but I feel like new FPGA suppliers coming around having open source tooling being the default is something that the authors of Yosys would like.

Zero ASIC even credited the original authors in the press release and released the source code, which they didn't need to do. If you release your code under a permissive license, like Yosys did, a company taking it and selling a closed source version of it is something you are allowing. If that's not something you want, choose a different license.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#25

Post by mschuster91 »

topspin wrote: post #10
polalavik wrote: post #4

Earlier quoted context omitted.

I know of a few vendor tools whose application size is measured in the multi-hundred of GBs

How does that happen? When I see this, I suspect the vendor is operating under conditions that approach absolute chaos: dumping whatever junk someone imagines might be necessary into the stack with zero resistance, for years on end. Zero effort spent on any factoring that might threaten redundancy.

Welcome to modern development lol. Try to refactor it and get an answer of "no money for testing".

On top of that, the "agile" mindset all too often also means there is no coherent vision where the project should go, which can and does lead to bad fundamental architecture decisions that need extensive and expensive workarounds later on.

And yes, there have been people describing exactly that in ASML [1], although the situation seems to have improved [2].

[1] https://news.ycombinator.com/item?id=23363938

[2] https://news.ycombinator.com/item?id=39465412

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#26

Post by rowanG077 »

elsjaako wrote: post #24
rowanG077 wrote: post #19

This is not a separate synthesis tool. This is just a yosys plugin and only works for their own FPGAs. Kind of leaves a bad taste in my mount that they choose to advertise this as their own synthesis tool when it isn't. I'm curious why they didn't work together with upstream. Also looking to their full stack it seem they use VPR/VTR instead of nextpnr for routing. That seems like a backwards choice.

When you release something as open source, a third party grabbing it and releasing it is explicitly something that can be done. I can't speak for them, so I'm not sure, but I feel like new FPGA suppliers coming around having open source tooling being the default is something that the authors of Yosys would like. Zero ASIC even credited the original authors in the press release and released the source code, which they…

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth.

In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#27

Post by wucke13 »

st_goliath wrote: post #8
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

I have dedicated a large chunk of my (arguably short) professional career on improving upon this, mostly in the safety critical software domain. What was your experience back then, what made you leave ultimately, and what do you do now?

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#28

Post by elsjaako »

rowanG077 wrote: post #26
elsjaako wrote: post #24

Earlier quoted context omitted.

When you release something as open source, a third party grabbing it and releasing it is explicitly something that can be done. I can't speak for them, so I'm not sure, but I feel like new FPGA suppliers coming around having open source tooling being the default is something that the authors of Yosys would like. Zero ASIC even credited the original authors in the press release and released the source code, which they…

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth. In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

I think we're reading the same article differently.

They start out by describing all the work that has been done by other people to make open source synthesis possible.

Then they say they've added some well known, industry standard optimizations to the existing open source tools. In addition, they made use of the abc tool in a way that maybe wasn't being done much before.

My view is that if you think someone taking your software, changing some parts, and releasing it under a different name (while still giving you credit in an about section) leaves a bad taste in your mouth, don't release your software with a permissive license. You are explicitly giving permission for someone to do this.

I don't like companies doing this, so I tend to release under GPL. Even then, I'm happy for someone to rebrand and sell it, as long as the source is still shared. I gave them permission to do that.

Don't give someone permission to do something, and then say it's in bad taste when they do that thing.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#29

Post by ACCount37 »

st_goliath wrote: post #8
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

It's much better in microcontrollers. Almost everything can now be handled with VSCode and some open source compiler toolchains.

PLCs and FPGAs are still pretty damn bad though.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#30

Post by RossBencina »

topspin wrote: post #10
polalavik wrote: post #4

Earlier quoted context omitted.

I know of a few vendor tools whose application size is measured in the multi-hundred of GBs

How does that happen? When I see this, I suspect the vendor is operating under conditions that approach absolute chaos: dumping whatever junk someone imagines might be necessary into the stack with zero resistance, for years on end. Zero effort spent on any factoring that might threaten redundancy.

I'm not saying the tools aren't bloated, but I believe that a lot of the size (sorry, can't quantify right now) are the datasets for each and every FPGA model that the tool supports. This includes, among other things, timing information for every wire in the chip. You really only need the files for the device that you are targeting and you do have the option to install only that, or you can install larger groups (e.g. same family, same generation), all the way up to installing every device that ever existed that the tool supports. That's how you get to hundreds of GB.
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