It's technically not 1-bit, but 2-bit. Anyway, I wonder if there is some HW support in modern CPUs/GPUs for linear algebra (like matrix multiplication) over Z_2^n ? I think it would be useful for SAT solving.
Or, technically, 1.58 bit. ;-)
1-Bit AI Infrastructure
21–30 of 33 posts
Re: 1-Bit AI Infrastructure
#22It seems like arxiv replaced 'bitnet.cpp' with a link 'this http url', even though '.cpp' is clearly not a tld. Poor regex?
> '.cpp' is clearly not a tld.
Is it that clear? Because e.g. .app and .cpa are TLDs. So are .py and .so.
Re: 1-Bit AI Infrastructure
#23I have read about it quite a few weeks ago the first time and I found it very interesting. Now that I have done more than enough CPU design inside FPGAs, I wanted to try something new, some computation heavy things that could benefit from an FPGA. Does anyone here know how feasable it'd be to implement something like that on an FPGA? I only have rather small chips (artix-7 35T and polarfire SoC with 95k logic slices)…
This submission should help you: https://news.ycombinator.com/item?id=41470074
Thanks!
Re: 1-Bit AI Infrastructure
#24Earlier quoted context omitted.
You gain in potential parallelism with FPGA, so with very small "at the edge" models they could speed things up, right? But the models are always going to be large, so memory bandwidth is going to be a bottle neck unless some v fancy FPGA memory "fabric" is possible. Perhaps for extremely low latency classification tasks? I'm having trouble picturing that application though. The code itself is surprisingly small/tigh…
> Perhaps for extremely low latency classification tasks? I'm having trouble picturing that application though. Possibly, yes. I have no concrete plans yet. Maybe language models are the wrong area though. Some general either image classification or object detection would be neat (say lane detection with a camera or something like that)
Real-time translation or speech transcription for the hearing-impaired onto AR-glasses? Now you've got a good reason to make it look like a Star Trek device.
Or glasses that can detect threats/opportunities in the environment and call them out via ear plugs, for the vision-impaired.
Re: 1-Bit AI Infrastructure
#25So basically the idea is to pack 3 ternary weights (-1,0,1) into 5 bits instead of 6, but they compare the results with fp16 model which would use 48 bits for those 3 weights…
And speed up comes from the memory io, compensated a bit by the need to unpack these weights before using them…
Did I get this right?
Re: 1-Bit AI Infrastructure
#26Does anyone have the actual "this http url"?
Re: 1-Bit AI Infrastructure
#27Does anyone have the actual "this http url"?
Re: 1-Bit AI Infrastructure
#28I have read about it quite a few weeks ago the first time and I found it very interesting. Now that I have done more than enough CPU design inside FPGAs, I wanted to try something new, some computation heavy things that could benefit from an FPGA. Does anyone here know how feasable it'd be to implement something like that on an FPGA? I only have rather small chips (artix-7 35T and polarfire SoC with 95k logic slices)…
I've had the same idea. One way to go about it would be to modify an existing RISC-V cpu to include the ternary math ops to accelerate bitnet operations. And vector/matrix extensions based on those. Then your LLM is implemented in RISC-V assembly using those extensions. (It would be possible to do some work on the LLVM backend so you could use a C implementation of the LLM, but that starts to be a lot of work. Also, we'd need 2 bit signed int types in C.)
A completely different approach is differentiable logic networks. You end up with a logic-gate network after training. This logic gate network would be very easy to translate into Verilog or VHDL. https://github.com/Felix-Petersen/difflogic
Re: 1-Bit AI Infrastructure
#29I have read about it quite a few weeks ago the first time and I found it very interesting. Now that I have done more than enough CPU design inside FPGAs, I wanted to try something new, some computation heavy things that could benefit from an FPGA. Does anyone here know how feasable it'd be to implement something like that on an FPGA? I only have rather small chips (artix-7 35T and polarfire SoC with 95k logic slices)…
You gain in potential parallelism with FPGA, so with very small "at the edge" models they could speed things up, right? But the models are always going to be large, so memory bandwidth is going to be a bottle neck unless some v fancy FPGA memory "fabric" is possible. Perhaps for extremely low latency classification tasks? I'm having trouble picturing that application though. The code itself is surprisingly small/tigh…
Lower latency, but also much lower power. This sort of thing would be of great interest to companies running AI datacenters (which is why Microsoft is doing this research, I'd think). Low latency is also quite useful for real-time tasks.
> The code itself is surprisingly small/tight. I'm been playing with llama.cpp for the last few days.
Is there a bitnet model that runs on llama.cpp? (looks like it: https://www.reddit.com/r/LocalLLaMA/comments/1dmt4v7/llamacp...) which bitnet model did you use?
Re: 1-Bit AI Infrastructure
#30So basically the idea is to pack 3 ternary weights (-1,0,1) into 5 bits instead of 6, but they compare the results with fp16 model which would use 48 bits for those 3 weights… And speed up comes from the memory io, compensated a bit by the need to unpack these weights before using them… Did I get this right?
Yeah, that seems to be the case. Though, I suspect Microsoft is interested in implementing something like a custom RISC-V CPU that has an ALU that's tuned for doing this ternary math and added custom vector/matrix instructions. Something like that could save them a lot of power in their data centers.
If it were to catch on then perhaps we'd see Intel, AMD, ARM adding math ops optimized for doing ternary math?