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I don't know how CPUs work so I simulated one in code (2019)

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Re: I don't know how CPUs work so I simulated one in code (2019)

#21

Post by cogman10 »

metaphor wrote: post #18
cogman10 wrote: post #4

So, what this project misses, which is quite hard to capture if you think of gates being just on off switches, is the fact that signals are not instantaneous, and everything runs in parallel. As the AND gate 4 gates up the chain switches the NOT gate 4 gates down the chain starts to send different and unstable signals which may or may not be interpreted as a 1 or 0 in the downstream gate. That's the reason computers…

> That's the reason computers have a clock, to make sure all transistors in a given stage of a CPU reach a steady state before moving on to the next instruction. Here I was thinking[1][2] the reason computers had clocks was merely a consequence of the synchronous architectures that characterize them. [1] https://en.wikipedia.org/wiki/Metastability_(electronics) [2] https://en.wikipedia.org/wiki/Quasi-delay-insensitiv…

What point are you trying to make?

You are correct that clock free designs exist. But calling it a mere consequence of sync design seems to be a misunderstanding of why sync design has a clock in the first place.

Re: I don't know how CPUs work so I simulated one in code (2019)

#23

Post by SoftTalker »

henrikschroder wrote: post #16

One of the most enlightening courses I took in university back in the day was digital electronics. Not because I ever wanted to muck about with it, but because we actually got to build our own super-simple physical 8-bit CPU. We had registers and an ALU and RAM and eight output leds, and we got to write the microcode for the fetch-execute cycle. Clock? There was a physical switch you would toggle on and off to make i…

Old minicomputers had toggle switches on the front panel where you could set the program counter, enter machine code instructions, and other things, as well as step the clock.

https://thumbs.worthpoint.com/zoom/images2/1/0619/05/vintage...

Re: I don't know how CPUs work so I simulated one in code (2019)

#24

Post by Tomte »

paranoidrobot wrote: post #10

I was once shown a dos-based CPU simulator back in the mid/late 90s. From memory it showed instruction decode, execution, cache and memory. Unfortunately I've never been able to find it, because all the google results are about running DOS games and/or DOSBox.

Mikrosim maybe? The name is because it simulates microcode. That was a huge a-ha moment for me in school.

https://en.wikipedia.org/wiki/MikroSim

http://www.mikrocodesimulator.de/index_eng.php

Re: I don't know how CPUs work so I simulated one in code (2019)

#26

Post by metaphor »

cogman10 wrote: post #21
metaphor wrote: post #18

Earlier quoted context omitted.

> That's the reason computers have a clock, to make sure all transistors in a given stage of a CPU reach a steady state before moving on to the next instruction. Here I was thinking[1][2] the reason computers had clocks was merely a consequence of the synchronous architectures that characterize them. [1] https://en.wikipedia.org/wiki/Metastability_(electronics) [2] https://en.wikipedia.org/wiki/Quasi-delay-insensitiv…

What point are you trying to make? You are correct that clock free designs exist. But calling it a mere consequence of sync design seems to be a misunderstanding of why sync design has a clock in the first place.

In the case of synchronous design patterns that handle metastability, it was to point out that the clock clearly isn't there "to make sure all transistors in a given stage of a CPU reach a steady state". The clock is there to invoke state transition, whereas achieving steady state is a function of satisfying setup/hold times; the former is fundamentally constrained by the latter.

In the case of QDI circuits, it was to point out that there exists CPUs which do not contain clocks, again challenging the assertion that the reason computers have clocks is "to make sure all transistors in a given stage of a CPU reach a steady state".

Re: I don't know how CPUs work so I simulated one in code (2019)

#27

Post by pyinstallwoes »

cogman10 wrote: post #4

So, what this project misses, which is quite hard to capture if you think of gates being just on off switches, is the fact that signals are not instantaneous, and everything runs in parallel. As the AND gate 4 gates up the chain switches the NOT gate 4 gates down the chain starts to send different and unstable signals which may or may not be interpreted as a 1 or 0 in the downstream gate. That's the reason computers…

But there exists clockless architectures.

Re: I don't know how CPUs work so I simulated one in code (2019)

#28

Post by rob74 »

Articles like this remind me of that one time I wrote a 6502 simulator in Turbo Pascal (complete with a primitive text mode disassembler where you could view and edit the machine code stored in memory) as a semester break project. It's of course very far from the complexity of today's CPUs, but basically they still work the same, and all of the optimizations of modern CPUs (pipelining, various cache levels, parallel execution, prefetch, branch prediction etc. etc. etc.) should be transparent to the user - of course, if you want to eke out the last bit of performance (targeting a specific CPU), it helps to be aware of all of that, but you don't need it for understanding how a CPU works.

Re: I don't know how CPUs work so I simulated one in code (2019)

#29

Post by tyingq »

pyinstallwoes wrote: post #27
cogman10 wrote: post #4

So, what this project misses, which is quite hard to capture if you think of gates being just on off switches, is the fact that signals are not instantaneous, and everything runs in parallel. As the AND gate 4 gates up the chain switches the NOT gate 4 gates down the chain starts to send different and unstable signals which may or may not be interpreted as a 1 or 0 in the downstream gate. That's the reason computers…

But there exists clockless architectures.

There's also things like a CMOS Z80 coupled with static ram. Where you still deal with propagation delay, but you can single step the clock and everything works like you expect. Mentioned, as it would fit pretty well in the code model the linked project implements.
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