21–30 of 163 posts
Even 10-15 years later, multiple CPUs and 128Mb RAM was quite uncommon. How much did this beast cost back in the 80s? Edit: Max configs were up to $250,000 ($663,937.02 today) back then according to this price list: http://www.bitsavers.org/pdf/apollo/Apollo_Price_List_Jul88....
Dual (50% overclocked) Celerons on a BP6 was a relatively common enthusiast setup in the early 2000s. 128M of RAM was also not a huge amount then.
I kept that thing running until 2008 or 2009. Great machine.
Makes this look like a truly artisan crafted machine -- lovingly crafted, all the way down to the documentation.
Wow, never heard of that ambitious CPU arch before. Looks like an early loser in the RISC wars that was recycled into later PA-RISC and Itanium. https://en.m.wikipedia.org/wiki/Apollo_PRISM
Wait a second.
So while this is all fancy and gives a better performance (with a mature compiler chuckles in Itanium)... but it's totally incompatible with virtualisation (as we know it on x86 systems)?
Cache trashing is surely always a way to throw out the performance, but this design would make it times worse, AFAIU?
Even 10-15 years later, multiple CPUs and 128Mb RAM was quite uncommon. How much did this beast cost back in the 80s? Edit: Max configs were up to $250,000 ($663,937.02 today) back then according to this price list: http://www.bitsavers.org/pdf/apollo/Apollo_Price_List_Jul88....
Wow, never heard of that ambitious CPU arch before. Looks like an early loser in the RISC wars that was recycled into later PA-RISC and Itanium. https://en.m.wikipedia.org/wiki/Apollo_PRISM
> In some respects, the VLIW design can be thought of as "super-RISCy", as it offloads the instruction selection process to the compiler as well. In the VLIW design, the compiler examines the code and selects instructions that are known to be "safe", and then packages them into longer instruction words. For instance, for a CPU with two functional units, like the PRISM, the compiler would find pairs of safe instructio…
Even though by the time I arrived we were mostly buying Sun, HP-PA, and Windows NT, the company started as an Apollo shop. And so SCM at HQ was based on Apollo DSEE ("dizzy"), which they liked, hence, DN10k servers scattered around.
https://bitsavers.org/pdf/apollo/008788-A01_Getting_Started_...
Wow, never heard of that ambitious CPU arch before. Looks like an early loser in the RISC wars that was recycled into later PA-RISC and Itanium. https://en.m.wikipedia.org/wiki/Apollo_PRISM
> In some respects, the VLIW design can be thought of as "super-RISCy", as it offloads the instruction selection process to the compiler as well. In the VLIW design, the compiler examines the code and selects instructions that are known to be "safe", and then packages them into longer instruction words. For instance, for a CPU with two functional units, like the PRISM, the compiler would find pairs of safe instructio…
Not that the Apollos actually had hardware support for virtualisation features such as nested page tables. These machines were from the days before virtualisation was popular. Only IBM mainframes had it back then AFAIK.
Earlier quoted context omitted.
Dual (50% overclocked) Celerons on a BP6 was a relatively common enthusiast setup in the early 2000s. 128M of RAM was also not a huge amount then.
Yes, I remember getting my Tualatin Celeron in 2003 with 256mb RAM. It was a beast compared to my friends machines at the time. :P
Tualatin for its over clockable head room. The Sempron for its oddly large L1 cache for the spec.
Nice enough CPU and memory. Not a very nice Unix experience, analogous to HP-UX it was complex, and a bugger to configure C code on if you came from BSD land (Ultrix, SunOS/Solaris)
Sockets felt like a badly coded bolt-on. They really wanted to pretend the internet protocol stack wasn't there.