Whilst I'm often quite sceptical of new HDLs (see my other comment on this post) it is nice to see HDL and other silicon content pop up so often on HN. There's a lot of keen people doing interesting things here and it's great to see all the new developments.
Filament – A Language for Fearless Hardware Design
21–30 of 34 posts
Re: Filament – A Language for Fearless Hardware Design
#22My experience with most "neo HDLs" is that they are all code generators which make the tedious part easy and don't really end up touching the hard part. This may be the first HDL I've seen that attempts to move the needle on catching bugs at compile time. (I've worked with several engineers, on hardware bugs which turned out to be pipelining errors, who did not understand what I meant by "make this design error inexp…
Every time I see one of these pop up, the thought that software engineers are forever trying to avoid knowledge, understanding, and wisdom with another layer of abstraction comes to mind. I’m all in favor of a better HDL. Verizon/SystemVerilog is loaded with completely non-obvious landmines. I’ve been doing this so long I forget they are there, but it’s pretty painful seeing someone new to the language step on them.…
> I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks.
I say this as an FPGA engineer that started my career in software: This used to be the case in software too. But we now have such good tools with REPLs, automatic tests, IDE integrations, partial implementation possibility that it's simply way less inefficient to build software like that.
I feel like that is precisely where the current hardware ecosystem stands. VHDL/Verilog/SV are simply not good enough to use it as a design exploration tool.
Instead of saying: "We use HDLs just to put in the design which we do beforehand" it should be "HDLs are the central tool in digital design. Both during design exploration and implementation". I think this is what people want out of these "neo" HDLs. The way you are viewing it is as only as a straightforward drop-in replacement. That is not what it's about.
Re: Filament – A Language for Fearless Hardware Design
#23Earlier quoted context omitted.
Every time I see one of these pop up, the thought that software engineers are forever trying to avoid knowledge, understanding, and wisdom with another layer of abstraction comes to mind. I’m all in favor of a better HDL. Verizon/SystemVerilog is loaded with completely non-obvious landmines. I’ve been doing this so long I forget they are there, but it’s pretty painful seeing someone new to the language step on them.…
> I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks. I say this as an FPGA engineer that started my career in software: This used to be the case in software too. B…
> during design exploration and implementation"
Assuming you meant to also include 'verification', then I can agree somewhat.
As an ASIC designer, you usually get just one stab at a hardware implementation, there's no 0-day point release. It's got to work so you spend the minimum time typing it in. Then you devote the maximum time to verifying it. I think some of the very poor quality s/w we are all subject to is partly due to a false sense of security that sw tooling provides. I expect fully working and efficient hardware, I'd like that from my software too, but in reality I rarely get that. The idea of applying more software dev processes/principles to hardware is a bit frightening to me.
Re: Filament – A Language for Fearless Hardware Design
#24I never really understand how HDL works. I meant, in software programming, we usually program by either specifying the sequence or dependency. In hardware, nothing runs sequentially, and signals propagate _with delay_. Everything happens at the same time, yet nothing run at the exact same moment. How could we express these chaos in for-loops and procedure look alikes?
Preface: My experience is in verilog so I'll mostly be coming from there. In most HDLs you have two kinds of code, procedural and continuous code. Your continuous code is wires which propagate signals and continuous logic (basically pure functions). Since there aren't any registers in this logic, that means you generally need to do timing analysis to make sure it never gets too long between any two given registers (o…
> continuous code
> continuous logic
This is terminology I'm used to. Generally this is called "combinational logic" in my experience. Is this a language or regional difference?
Re: Filament – A Language for Fearless Hardware Design
#25Earlier quoted context omitted.
Every time I see one of these pop up, the thought that software engineers are forever trying to avoid knowledge, understanding, and wisdom with another layer of abstraction comes to mind. I’m all in favor of a better HDL. Verizon/SystemVerilog is loaded with completely non-obvious landmines. I’ve been doing this so long I forget they are there, but it’s pretty painful seeing someone new to the language step on them.…
> I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks. I say this as an FPGA engineer that started my career in software: This used to be the case in software too. B…
I'm also an FPGA person that started off in software and this is exactly how I feel, and the reason I'm building my own HDL too. Software languages have evolved so much since the 80s and are so much more productive, HDLs have missed out on that, but convincing hardware engineers about that is an uphill battle
Re: Filament – A Language for Fearless Hardware Design
#26Earlier quoted context omitted.
Every time I see one of these pop up, the thought that software engineers are forever trying to avoid knowledge, understanding, and wisdom with another layer of abstraction comes to mind. I’m all in favor of a better HDL. Verizon/SystemVerilog is loaded with completely non-obvious landmines. I’ve been doing this so long I forget they are there, but it’s pretty painful seeing someone new to the language step on them.…
But couldn't there be languages where it was easier to express that design? Your description reminds me what it's like to program in C.
I love how this is being downvoted! Writing Verilog or VHDL is exactly like writing C, or maybe even assembly
Re: Filament – A Language for Fearless Hardware Design
#27My experience with most "neo HDLs" is that they are all code generators which make the tedious part easy and don't really end up touching the hard part. This may be the first HDL I've seen that attempts to move the needle on catching bugs at compile time. (I've worked with several engineers, on hardware bugs which turned out to be pipelining errors, who did not understand what I meant by "make this design error inexp…
I think I don't understand how to make a design error inexpressible either.
I know what the statement means, but I fail to imagine any hardware construction that is automatically wrong, merely ones that don't do what someone wanted. The same exact construct and resulting behavior could be what someone else wanted.
Violating the nominal specs, or the nominal intended purpose of a part or circuit to get particular results is the oldest thing in the world.
Maybe some things are common enough that it's reasonable to make them difficult to express?
Ok, also especially if you can assert your intentions with labels that say high level things, then I guess I can see being able to flag some things that would break the intentions expressed by the labels.
Maybe I'm starting to imagine a little.
Re: Filament – A Language for Fearless Hardware Design
#28Earlier quoted context omitted.
> I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks. I say this as an FPGA engineer that started my career in software: This used to be the case in software too. B…
> during design exploration and implementation" Assuming you meant to also include 'verification', then I can agree somewhat. As an ASIC designer, you usually get just one stab at a hardware implementation, there's no 0-day point release. It's got to work so you spend the minimum time typing it in. Then you devote the maximum time to verifying it. I think some of the very poor quality s/w we are all subject to is par…
> Assuming you meant to also include 'verification', then I can agree somewhat.
This project involves static verification of one part of hardware design, namely the timing properties of pipelines and sequential circuits.
This is not all of verification (which is a huge issue in modern semiconductor design) or even of high-level design verification, but it probably helps.
Re: Filament – A Language for Fearless Hardware Design
#29Earlier quoted context omitted.
Preface: My experience is in verilog so I'll mostly be coming from there. In most HDLs you have two kinds of code, procedural and continuous code. Your continuous code is wires which propagate signals and continuous logic (basically pure functions). Since there aren't any registers in this logic, that means you generally need to do timing analysis to make sure it never gets too long between any two given registers (o…
> continuous code > continuous logic This is terminology I'm used to. Generally this is called "combinational logic" in my experience. Is this a language or regional difference?
Oh nah I just wrote it at like 2am.
Re: Filament – A Language for Fearless Hardware Design
#30html { font-weight: 100; }
Can we please stop with illegible text? Color: 333 indeed.