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TinyEMU – x86 and RISC-V emulator, small and simple while being complete

bellard.org

21–30 of 32 posts

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#21
post #20
post #8

Earlier quoted context omitted.

B extension was ratified in 2021, near the end. It is considerably newer than every extension this emulator implements, and thus reasonable it'd have these and not B.

Hopefully B becomes ubiquitous in the next generation of SoC's, or RISC-V is going to look bad in any benchmarks that happen to have a popcnt in the hot path.

At least Zba, Zbb and Zbs are in RVA22 iirc.

edit: Zbs.

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#22
post #21
post #20

Earlier quoted context omitted.

Hopefully B becomes ubiquitous in the next generation of SoC's, or RISC-V is going to look bad in any benchmarks that happen to have a popcnt in the hot path.

At least Zba, Zbb and Zbs are in RVA22 iirc. edit: Zbs.

Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#23
post #20
post #8

Earlier quoted context omitted.

B extension was ratified in 2021, near the end. It is considerably newer than every extension this emulator implements, and thus reasonable it'd have these and not B.

Hopefully B becomes ubiquitous in the next generation of SoC's, or RISC-V is going to look bad in any benchmarks that happen to have a popcnt in the hot path.

I worry a bit that B is too ambitious with many instructions that no one is using yet which are difficult to prove their value as a result, while regular RISC-V is essentially hobbled compared to ordinary cpus due to the absence of popcnt/clz.

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#24
post #21
post #20

Earlier quoted context omitted.

Hopefully B becomes ubiquitous in the next generation of SoC's, or RISC-V is going to look bad in any benchmarks that happen to have a popcnt in the hot path.

At least Zba, Zbb and Zbs are in RVA22 iirc. edit: Zbs.

Zbc (carryless multiply) seems to be needed to implement AES-GCM

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#25
post #21

Earlier quoted context omitted.

At least Zba, Zbb and Zbs are in RVA22 iirc. edit: Zbs.

Zbc (carryless multiply) seems to be needed to implement AES-GCM

It is required in Zkn (Scalar Crypto NIST Algorithms) and Zks (Scalar Crypto ShangMi Algorithms).

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#26
post #20
post #8

Earlier quoted context omitted.

B extension was ratified in 2021, near the end. It is considerably newer than every extension this emulator implements, and thus reasonable it'd have these and not B.

Hopefully B becomes ubiquitous in the next generation of SoC's, or RISC-V is going to look bad in any benchmarks that happen to have a popcnt in the hot path.

>Hopefully B becomes ubiquitous in the next generation of SoC's

Hopefully together with V.

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#27
post #15

Earlier quoted context omitted.

The soon to be released VisionFive 2 board seems like a good match https://www.starfivetech.com/en/site/boards

That's significantly more overkill than the D1.

The D1 based miniboards seem to be the currently only alternative for what I would like to do. Only the mango pi board I guess, or any others?

I could not confirm if the k210 has a usb controller (not the UARTUSB dongle).

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#28
post #23
post #20

Earlier quoted context omitted.

Hopefully B becomes ubiquitous in the next generation of SoC's, or RISC-V is going to look bad in any benchmarks that happen to have a popcnt in the hot path.

I worry a bit that B is too ambitious with many instructions that no one is using yet which are difficult to prove their value as a result, while regular RISC-V is essentially hobbled compared to ordinary cpus due to the absence of popcnt/clz.

Most implementations announced recently (e.g. in RISC-V Summit last December) have B.

Even the newer revisions of cores that have been available for a while (like SiFive U74) have been updated with B support.

As such, I believe it to be a non-issue. Hardware simply takes time.

>which are difficult to prove their value as a result,

As with any RISC-V extensions, each instruction had to meet many criteria to be allowed in there.

Rationale accompany the instructions in the documentation.

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#29
post #27
post #15

Earlier quoted context omitted.

That's significantly more overkill than the D1.

The D1 based miniboards seem to be the currently only alternative for what I would like to do. Only the mango pi board I guess, or any others? I could not confirm if the k210 has a usb controller (not the UART USB dongle).

See the list of boards part of the D1 article[0] in linux-sunxi wiki. There are at least 5 options listed.

Lichee RV (with a breakout dock board) is the one I have.

https://linux-sunxi.org/D1

Re: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

#30

https://bellard.org/tinyemu/readme.txt : > 4.1) 128 bit support > The RISC-V specification does not define all the instruction encodings for the 128 bit integer and floating point operations. The missing ones were interpolated from the 32 and 64 ones. > Unfortunately there is no RISC-V 128 bit toolchain nor OS now (volunteers for the Linux port ?), so rv128test.bin may be the first 128 bit code for RISC-V !

lol, that's a brave approach.

Although with my pedant hat on: that's extrapolation, not interpolation. That's because 128 is outside of the existing range.

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