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AMD Alveo V70 AI inference accelerator card

xilinx.com

21–30 of 94 posts

Re: AMD Alveo V70 AI inference accelerator card

#22
post #19

Douglas Adams said we'd have robots to watch TV for us. That seems to be the designed use case for this. 16gb RAM / 96 video channels ... I haven't done any of that work but it feels like they expect that "96" not to be fully used in practice.

I have no problem imagining a security camera application needing to monitor quite a few video channels.

/camera/state/g

Re: AMD Alveo V70 AI inference accelerator card

#23
post #16

AMD XDNA – Versal AI Core / 2nd-gen AIE-ML tiles Are these programmable by the end-user? The "software programmability" section describes "Vitis AI" frameworks supported. But can we write our own software on these? Is this card FPGA-based? EDIT: [1] more info on the AI-engine tiles: scalar cores + "adaptable hardware (FPGA?)" + {AI+DSP}. [1] https://www.xilinx.com/products/technology/ai-engine.html

It's very likely FPGA-based; Xilinx is an FPGA company. This is being pitched as an "AI accelerator", but "Alveo" as a product line existed before AMD's acquisition of Xilinx, and other "Alveo" products exist ( https://www.xilinx.com/products/boards-and-kits/alveo.html ) that are marketed for other purposes, while really just being Xilinx FPGAs pre-programmed to perform specific other tasks, with some domain-specific…

It's not a traditional FPGA chip (lots of luts and flip flops). The "AI Engine" is basically hardened chiplets that are working alongside soft logic chiplets and I/O. This is how they're able to get their performance/power numbers

Re: AMD Alveo V70 AI inference accelerator card

#25
post #19

Douglas Adams said we'd have robots to watch TV for us. That seems to be the designed use case for this. 16gb RAM / 96 video channels ... I haven't done any of that work but it feels like they expect that "96" not to be fully used in practice.

I have no problem imagining a security camera application needing to monitor quite a few video channels.

Certainly. I'm suspecting that doing much of anything with all 96 channels would really need more RAM, for most users.

Re: AMD Alveo V70 AI inference accelerator card

#26
post #23
post #16

Earlier quoted context omitted.

It's very likely FPGA-based; Xilinx is an FPGA company. This is being pitched as an "AI accelerator", but "Alveo" as a product line existed before AMD's acquisition of Xilinx, and other "Alveo" products exist ( https://www.xilinx.com/products/boards-and-kits/alveo.html ) that are marketed for other purposes, while really just being Xilinx FPGAs pre-programmed to perform specific other tasks, with some domain-specific…

It's not a traditional FPGA chip (lots of luts and flip flops). The "AI Engine" is basically hardened chiplets that are working alongside soft logic chiplets and I/O. This is how they're able to get their performance/power numbers

I suspect that it still has some fpga fabric attacched to the ai engines. The two parts are separate, but according to Xilinx docs (talking about Versal Soc), they are supposed to work togheter

Re: AMD Alveo V70 AI inference accelerator card

#27
post #16

AMD XDNA – Versal AI Core / 2nd-gen AIE-ML tiles Are these programmable by the end-user? The "software programmability" section describes "Vitis AI" frameworks supported. But can we write our own software on these? Is this card FPGA-based? EDIT: [1] more info on the AI-engine tiles: scalar cores + "adaptable hardware (FPGA?)" + {AI+DSP}. [1] https://www.xilinx.com/products/technology/ai-engine.html

It's very likely FPGA-based; Xilinx is an FPGA company. This is being pitched as an "AI accelerator", but "Alveo" as a product line existed before AMD's acquisition of Xilinx, and other "Alveo" products exist ( https://www.xilinx.com/products/boards-and-kits/alveo.html ) that are marketed for other purposes, while really just being Xilinx FPGAs pre-programmed to perform specific other tasks, with some domain-specific…

[deleted]

Re: AMD Alveo V70 AI inference accelerator card

#28
post #19

Douglas Adams said we'd have robots to watch TV for us. That seems to be the designed use case for this. 16gb RAM / 96 video channels ... I haven't done any of that work but it feels like they expect that "96" not to be fully used in practice.

I have no problem imagining a security camera application needing to monitor quite a few video channels.

>> I have no problem imagining a security camera application needing to monitor quite a few video channels.

As a joke I sometimes tell people the automatic flushing toilets in public bathrooms work by having a little camera monitored by someone in a 3rd world country who remotely flushes as needed, while monitoring a whole lot of video feeds. They usually don't buy it, but will often acknowledge that our world is uncomfortably close to having stuff like become reality.

Re: AMD Alveo V70 AI inference accelerator card

#29
post #18
post #13

> High-Density Video Decoder**: 96 channels of 1920x1080p > [...] > **: @10 fps, H.264/H.265 Is 10 fps a standard measure for this kind of thing?

10 fps should be fast enough to provide input tensors for real time inference with small scale transformers / convolutional nets.

Maybe. Running inference at 10 fps is probably plenty. But that doesn't mean you only have to do 10 fps of H.264/H.265 decoding. I think the most common scenario is for the input video to be e.g. 30 fps with mostly P frames that each depend on the prior frame in a chain. In that case, you need to decode almost [1] 30 fps to get 10 fps of evenly spaced frames to process.

[1] You could skip the last P frame before an IDR frame, but that doesn't buy you much.

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