21–30 of 81 posts
What is extremely telling is what is missing ... Design Rule Checking (DRC) and Layout Vs Schematic (LVS). These require: 1) Longer bit length arithmetic 32-bit float simply isn't enough. 64-bit float is close, but limited. You really want 128-bit integer. And nVidia isn't delivering that. 2) Real algorithmic improvements We're still stuck with computational geometry algorithms that don't parallelize. It would be awf…
What is extremely telling is what is missing ... Design Rule Checking (DRC) and Layout Vs Schematic (LVS). These require: 1) Longer bit length arithmetic 32-bit float simply isn't enough. 64-bit float is close, but limited. You really want 128-bit integer. And nVidia isn't delivering that. 2) Real algorithmic improvements We're still stuck with computational geometry algorithms that don't parallelize. It would be awf…
> You really want 128-bit integer. And nVidia isn't delivering that. How much slower (per unit area) is that to do in software, compared to a full 128-bit hardware unit?
See:
https://developer.nvidia.com/blog/cuda-11-6-toolkit-new-rele... https://developer.nvidia.com/blog/implementing-high-precisio...
Earlier quoted context omitted.
> but it's also extremely NVidia that they're doing it all on their own. Having a lead in chip design is their literal bread and butter. I think it's extremely "publicly traded company" more than "NVidia". Do you have an example of a company releasing an open source version of their secret sauce (foundation of their profits)?
> Do you have an example of a company releasing an open source version of their secret sauce? The chip design itself should be the secret sauce. Not the tools you make the chip with. Nvidia is resolutely not-contributing. Many other companies are starting to get onboard with open chip design. This doesn't mean the chips have to be open, but the tooling needs to be something shared & co-developable. If this is a littl…
Earlier quoted context omitted.
> but it's also extremely NVidia that they're doing it all on their own. Having a lead in chip design is their literal bread and butter. I think it's extremely "publicly traded company" more than "NVidia". Do you have an example of a company releasing an open source version of their secret sauce (foundation of their profits)?
> Do you have an example of a company releasing an open source version of their secret sauce? The chip design itself should be the secret sauce. Not the tools you make the chip with. Nvidia is resolutely not-contributing. Many other companies are starting to get onboard with open chip design. This doesn't mean the chips have to be open, but the tooling needs to be something shared & co-developable. If this is a littl…
All these aspects are part of the chip design, and being bad at one can significantly compromise the competitiveness of the final piece of silicon.
So this statement is hopelessly naive and ignorant:
> The chip design itself should be the secret sauce. Not the tools you make the chip with.
Because all the steps that I listed above are done with tools. And in many cases, having better tools is the secret sauce that makes your design better than the competition.
The article mentions a runtime of minutes instead of a day to do IR drop checking: that's the kind of acceleration that allows trying out multiple configurations for an optimal solution instead of settling for good enough. A lower amount of IR drop allows for a more aggressive, less conservative power curve. End result: a chip that can be clocked at a higher speed without needing to increase the voltage. A major competitive advantage.
> are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion?
Of course there are. AI can be used for almost anything where large amount of data is already available, and where there's a clear cost function that must be optimized. AI is a natural for many steps in the ASIC design flow. You could have figured this out by yourself: Nvidia is talking about it. If it were such a big novelty, they'd keep it under wraps.
> WD's Swerv RISC-V core for their driver controller ARM R-series replacement [snip snip] everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth.
Let's talk Swerv: a piece of IP that's definitely useful to Western Digital. Useful to general world too. But not something that scores particularly high on the list of the secret sauce ingredients that makes or breaks their products. Does Nvidia have similar open source IP offerings? Yes, they do! Check out NvDLA: Nvidia's open source DL accelerator. Your day must be a whole lot better now, knowing that, just like WD, Nvidia also open sources some non-critical IP.
I'm sure that you're aware that AMD uses a neural network in their CPU branch predictor. Do you think that AMD should release the tool that was used to figure out the optimal weights? After all, the tool itself is not part of the actual CPU design...
the last time I checked autorouters were still not capable of doing all the routing on a multi layer PCB properly, and manual work was still required to produce a decent design.
I hope you don't have the idea that chip routing is done manually.
the last time I checked autorouters were still not capable of doing all the routing on a multi layer PCB properly, and manual work was still required to produce a decent design.
How is that a relevant comment in a discussion about ASIC design? I hope you don't have the idea that chip routing is done manually.
I worked on MCU layout around 2011, and only the digital logic was autorouted/placed.
What is extremely telling is what is missing ... Design Rule Checking (DRC) and Layout Vs Schematic (LVS). These require: 1) Longer bit length arithmetic 32-bit float simply isn't enough. 64-bit float is close, but limited. You really want 128-bit integer. And nVidia isn't delivering that. 2) Real algorithmic improvements We're still stuck with computational geometry algorithms that don't parallelize. It would be awf…
“Is the minimal distance between all metal routing > 10 nm” etc.
Can you explain why high precision is needed for that?
the last time I checked autorouters were still not capable of doing all the routing on a multi layer PCB properly, and manual work was still required to produce a decent design.
How is that a relevant comment in a discussion about ASIC design? I hope you don't have the idea that chip routing is done manually.
Earlier quoted context omitted.
How is that a relevant comment in a discussion about ASIC design? I hope you don't have the idea that chip routing is done manually.
Are the analog parts (current nitrist etc) autorouted now? I worked on MCU layout around 2011, and only the digital logic was autorouted/placed.