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Samsung Foundry Forum announcements

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Re: Samsung Foundry Forum announcements

#21
post #2

At what point does quantum tunnelling become a problem?

First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particula…

>but it was in the past two decades and got particularly ridiculous beginning around "28nm" up to now.

I wonder if that is some kind of cultural shift that is taking place that started around 2009, or if it's always been like this and I just never noticed.

BMW model numbers used to more or less accurately reflect engine sizes, not anymore, it's just numbers now.

2G, 3G, 4G used to mean something, not anymore.

I could add a remark about the federal reserve, but... I'll just stay away from that. Don't want to be too edgy/turn this into a political discussion (I just think it's interesting from a cultural perspective).

It's like we collectively decided that "it's just numbers, man."

Re: Samsung Foundry Forum announcements

#22
post #12

Earlier quoted context omitted.

The theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm. You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.

Can't they use a smaller wavelength source? Nothing special about 13nm afaik

13nm is hard enough. ASML seems to have settled on laser-driven tin plasma light source, which is miserably inefficient: https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph

>The required utility resources are significantly larger for EUV compared to 193 nm immersion, even with two exposures using the latter. Hynix reported at the 2009 EUV Symposium that the wall plug efficiency was ~0.02% for EUV, i.e., to get 200-watts at intermediate focus for 100 wafers-per-hour, one would require 1-megawatt of input power

The optical train is also tough. 13nm is getting close to soft x-rays, and photons that hot don't like reflecting, and the optics are rapidly degraded by exposure light:

>EUV collector reflectivity degrades ~0.1-0.3% per billion 50kHz pulses (~10% in ~2 weeks), leading to loss of uptime and throughput [...] Due to the use of EUV mirrors which also absorb EUV light, only a small fraction of the source light is finally available at the wafer. There are 4 mirrors used for the illumination optics, and 6 mirrors for the projection optics. The EUV mask or reticle is itself an additional mirror. With 11 reflections, only ~ 2% of the EUV source light is available at the wafer.

Re: Samsung Foundry Forum announcements

#23

There are a few comments saying that 3nm is a marketing term and that the transistors are actually larger - how is this allowed? Isn't it misleading and deceptive?

Well, I hope nobody chooses a fab based on the headline number on their marketing material. Adapting your design to them is a long process that requires all kinds of details, and how well they will produce your circuit depends on those details as much as on the feature size.

Re: Samsung Foundry Forum announcements

#24

Earlier quoted context omitted.

Can't they use a smaller wavelength source? Nothing special about 13nm afaik

The design of EUV lasers is already completely absurd. It's an awesome piece of engineering, but it's no easier to push the laser wavelength downwards than anything else.

Does the lithography require the tight wavelength or other nice properties of lasers? I had thought they used filtered synchrotron output since a while ago.

Basically everything about the process is absurd, not sure why pushing on the light source is less feasible then any of the other knobs

Re: Samsung Foundry Forum announcements

#25
post #6

I can never remember what xnm means as it varies between companies. In this case, Samsung's 3nm = Intel's 7nm I am still waiting for a standard based on transistor density numbers!

Intel actually renamed their nodes in like with Samsung and TSMC, so Intel 7 (used to called 10nm) is roughly comparable to TSMCs 7nm and Samsungs 8nm

For anyone who had not been aware (like me), apparently Intel has renamed their third gen 10 nm process to 7, and their 7 nm process (the one that they describe as being their first full use of EUV, that got pushed back to 2023) is now named 4. That puts Intel’s node naming roughly in line with TSMC and Samsung in terms of feature density.

Re: Samsung Foundry Forum announcements

#26
post #20

Samsung has a dishonorable marketing department. 3nm is not actually 3nm. I'm fed up... OLED is superior so they had to take the path of calling theirs QLED which is actually just an LCD screen with phosphors on top of a blue backlight (and it's nothing new).

> 3nm is not actually 3nm

It's a stretch to blame that on Samsung, processor generations described in nanometres haven't been based on actual component size for years now, by any manufacturer.

Re: Samsung Foundry Forum announcements

#27

At what point do we have to stop because we’ve hit physical limits? At 3nm we are talking transistors only a few dozen atoms wide, what’s the smallest theoretical transistor we can build?

With the old-school plane transistors over the wafer's silicon design, you need about 10nm of doped material so it won't completely mix with everything else.

With theoretical organic 1-electron designs you can build a transistor out of 4 carbon atoms. But nobody knows how to mass produce those ones.

We are somewhere on the middle, modern designs did break the 10nm barrier, but are not nearly as small as those numbers you see around.

Re: Samsung Foundry Forum announcements

#28

Earlier quoted context omitted.

First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particula…

>but it was in the past two decades and got particularly ridiculous beginning around "28nm" up to now. I wonder if that is some kind of cultural shift that is taking place that started around 2009, or if it's always been like this and I just never noticed. BMW model numbers used to more or less accurately reflect engine sizes, not anymore, it's just numbers now. 2G, 3G, 4G used to mean something, not anymore. I could…

>It's like we collectively decided that "it's just numbers, man."

People with no scruples realized it's easier/cheaper to confuse and persuade people something is better than actually producing something better and that conventional wisdom was wrong.

It's a lot easier to invest in propoganda that convinced improved perceived value than actual value. It's win-win, the consumer thinks they're happy and the producer doesn't have to deal with the mess of hurdles in reality to continue to make money. Conventional wisdom says people are smart and will see through your snake oil, meanwhile, empirical data says people will drink the snake oil if you tell them it's from the fountain of youth.

Re: Samsung Foundry Forum announcements

#29
post #20

Samsung has a dishonorable marketing department. 3nm is not actually 3nm. I'm fed up... OLED is superior so they had to take the path of calling theirs QLED which is actually just an LCD screen with phosphors on top of a blue backlight (and it's nothing new).

And cpus are just sand

Re: Samsung Foundry Forum announcements

#30
post #20

Samsung has a dishonorable marketing department. 3nm is not actually 3nm. I'm fed up... OLED is superior so they had to take the path of calling theirs QLED which is actually just an LCD screen with phosphors on top of a blue backlight (and it's nothing new).

What is the best metric nowadays? Dhrystones/MIPS/FLOPS per MHz/Watt per square inch? As a complete outsider, millions of transistors per square inch sounds like a very intuitive metric of how small things are.
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