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Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

openpowerfoundation.org

21–30 of 68 posts

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#21

A fully open source chip, from Verilog to Fabrication is cool! It may be 180nm (1999-era technology), but that's still hugely important. The world of semiconductor design is incredibly closed source and secretive.

What about the tools and processes to manufacture this? Are those open source or broadly available? For instance, is it possible to have a small scale "community" fab for 1999-era chip technology?

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#22
> Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout

In other words, this chip isn't even remotely open-source.

What they sent to the foundry isn't the "ghost cells" (which don't have transistors in them and therefore don't work).

This fails the most basic requirements of being open source.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#23
post #20

Earlier quoted context omitted.

Note that Google has open sourced a full set of design rules for a 130nm process (codenamed SkyWater), making fully open chip designs also possible for this finer process. 130nm was current in the very early 2000s, so it should be possible to achieve interesting results with it.

Didn't they require some closed logic between your stuff and all of the I/O?

Yes, and they still do. They've got a Management-Engine type layer that you are forbidden to remove or modify in any way, even if you pay the full $10k and do not accept any subsidies.

So many people asked about this that the foundry had to make a FAQ about it:

https://www.skywatertechnology.com/ufaqs/can-i-customize-the...

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#24
post #16

For SW type people ... GCC's impact was possible because it was (with GAS - the assembler) 100% feasible to have an open source toolchain. Yes more software was necessary for a complete system (linker, libc, etc), but GCC made it possible to build from the ground floor up. Also, yes, the initial GCC was worse than any proprietary decent tool chain at the time, but it got better and better because each improvement bui…

I've worked on big chips designed to be taped out to multiple (3) fabs - you have to either build your own libraries that have some minimum performance on all processes, or recompile with a new fab's libraries - my experience is that if you plan for it it's more a matter of a few months than years

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#26

A fully open source chip, from Verilog to Fabrication is cool! It may be 180nm (1999-era technology), but that's still hugely important. The world of semiconductor design is incredibly closed source and secretive.

What about the tools and processes to manufacture this? Are those open source or broadly available? For instance, is it possible to have a small scale "community" fab for 1999-era chip technology?

Or any other options for "small" batch sizes?

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#27
post #5

This is a very important step. I don't understand how this is not on the first page. Maybe a more click-baity title is needed?

Who is this important for? Is there a lot of software still being developed for POWER? It seems niche to me, but maybe I'm the one in a niche.

Many hyperscalar server setups use POWER8/POWER9 CPUs. 4 logical processes per core (and 8 with the upcoming 15-core POWER10 configurations) are pretty useful when measuring perf-per-watt.

The Talos is currently the only fully libre computer available for high-perf computing, and it uses POWER9 CPUs. If you want a fully free CPU, your choices are either very dated CPUs or POWER.

Many distros (inc. Debian, and most source-based ones) support ppc64/POWER officially quite well and go out of their way to ensure a high degree of portability.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#28
post #20

Earlier quoted context omitted.

Didn't they require some closed logic between your stuff and all of the I/O?

Yes, and they still do. They've got a Management-Engine type layer that you are forbidden to remove or modify in any way, even if you pay the full $10k and do not accept any subsidies. So many people asked about this that the foundry had to make a FAQ about it: https://www.skywatertechnology.com/ufaqs/can-i-customize-the...

This impacts the fab itself, but the design rules can still be usable elsewhere since they've been released openly.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#29

A fully open source chip, from Verilog to Fabrication is cool! It may be 180nm (1999-era technology), but that's still hugely important. The world of semiconductor design is incredibly closed source and secretive.

What about the tools and processes to manufacture this? Are those open source or broadly available? For instance, is it possible to have a small scale "community" fab for 1999-era chip technology?

I've been keeping an eye out for anything like this. There's Sam Zeloof, doing one-offs in his home lab [1], and there's Libre Silicon [2] putting together their fab too, but the info there's more scarce.

Neither one has published an easily-replicable process, meaning I can't really repeat what they've done. IMO what this space needs is an open source build plan/BoM, with a cottage industry of people selling DiY and pre-assembled kits. Once the 3d printing community got there, that's when things took off -- before kits or at least build guides with proper BoMs, it was just disparate individuals doing their own thing.

Connect me with anyone who's got a good approach to building some sort of replicable open-source fab though, and I'll quit my job and join the project full-time (that's not a joke: I'm serious).

[1] http://sam.zeloof.xyz/category/semiconductor/ [2] https://libresilicon.com/

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#30
post #7

What does this mean to noobs like me?

Here are a few implications:

* In a few years (maybe 5?), it might be possible to build a computer that you can trust has no intentional back doors in the CPU, but is modern enough to run software from within the last decade.

* If this catches on, and is used by enough people, economies of scale might kick in, and bring costs for advanced custom chips down by an order of magnitude (if the cpu is small enough, and if more fab capacity is built). Not Intel/AMD/ARM parts - those prices will remain stable, at first.

* Maybe we can have another decent consumer-grade router? No, this is a pipe-dream.

* Our Amiga accelerator boards will become SMOKING fast.

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