Earlier quoted context omitted.
AHCI supports DMA, which has been the preferred transfer standard in ATA since the mid-1990s. Nobody in their right mind would intentionally use the PIO modes except on very very old hardware. And for a device that can handle 320,000+ IOPS, a short queue depth won't be a bottleneck.
Sorry, I meant that AHCI requires the driver to do a PIO read to set up each command, even though the data is transferred using DMA. This card has 32 flash channels and 128 or more NAND dies, so a queue depth of 32 would leave most of the dies idle.
I'm not sure it's relevant. Queueing in the transfer protocol is a useful feature to address the limitations of physical hard disks (i.e., to delegate the ordering of temporally-proximate I/O operations to the device, which usually can do it better than the host OS can). With flash disks, optimization of seeks is unnecessary (since there are no seeks), and they are usually so fast that the command queues rarely grow.