It looks like you're using an ice40 FPGA? If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface: https://github.com/efabless/caravel/blob/master/verilog/rtl/... The openlane tool converts your verilog all the way down to final ASIC design... You'd need…
I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
21–30 of 52 posts
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#22Earlier quoted context omitted.
Yes, I'm using Wyre for this. Feedback is always welcome, so once you've had a chance to try it, don't hesitate to let me know what you think!
Wow! This is really cool, thank you for open sourcing this! Do you have any posts talking about how you got started with FPGAs? I'm a SWE and want to get into this area. Your language seems to map directly to what I was sort of expecting to see in the HDL/VHDL world but wasn't finding. You're making me want to buy a VGA monitor and an iCE.
In terms of hardware, I'm using an iCEBreaker dev board [1] which has worked really well (A nice bonus is that the board has a 16MB flash chip, which can be used for storage -- this is what the Minecraft clone uses to load the map and textures from on startup).
On the software side, I'm using the open source yosys/nextpnr/icestorm toolchain which is a lot faster than the vendor supplied tools. I mostly figured things out by just trying stuff, so a high iteration speed definitely helped here!
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#23It looks like you're using an ice40 FPGA? If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface: https://github.com/efabless/caravel/blob/master/verilog/rtl/... The openlane tool converts your verilog all the way down to final ASIC design... You'd need…
In terms of I/O pins that should actually be fine (current pinout: VGA (14x), SPI (4x), CLK (1x), N64_controller (1x)), though I'm still working on the project and I don't think it'll be done by the deadline. It looks like they might do future batches though -- it's a cool idea!
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#24Earlier quoted context omitted.
Wow! This is really cool, thank you for open sourcing this! Do you have any posts talking about how you got started with FPGAs? I'm a SWE and want to get into this area. Your language seems to map directly to what I was sort of expecting to see in the HDL/VHDL world but wasn't finding. You're making me want to buy a VGA monitor and an iCE.
Just do it ;). I don't have a blog post on how I got started, but you gave me the idea that perhaps I should write one. In terms of hardware, I'm using an iCEBreaker dev board [1] which has worked really well (A nice bonus is that the board has a 16MB flash chip, which can be used for storage -- this is what the Minecraft clone uses to load the map and textures from on startup). On the software side, I'm using the op…
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#25It looks like you're using an ice40 FPGA? If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface: https://github.com/efabless/caravel/blob/master/verilog/rtl/... The openlane tool converts your verilog all the way down to final ASIC design... You'd need…
In terms of I/O pins that should actually be fine (current pinout: VGA (14x), SPI (4x), CLK (1x), N64_controller (1x)), though I'm still working on the project and I don't think it'll be done by the deadline. It looks like they might do future batches though -- it's a cool idea!
Unless you're particularly fond of the N64's controller design that is
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#26Earlier quoted context omitted.
In terms of I/O pins that should actually be fine (current pinout: VGA (14x), SPI (4x), CLK (1x), N64_controller (1x)), though I'm still working on the project and I don't think it'll be done by the deadline. It looks like they might do future batches though -- it's a cool idea!
If you're using an n64 controller, you might want to consider using a gamecube one instead (it uses the same control logic, it just adds a 5v line for rumble features) Unless you're particularly fond of the N64's controller design that is
[1] https://www.raphnet-tech.com/products/gc_controller_connecto...
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#27Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#28Earlier quoted context omitted.
If you're using an n64 controller, you might want to consider using a gamecube one instead (it uses the same control logic, it just adds a 5v line for rumble features) Unless you're particularly fond of the N64's controller design that is
That's a good idea. The two analog sticks on the GC controller would be an improvement over the single stick on the N64 controller for movement in 3D. I think that the main benefit of the N64 controller (besides a nostalgia factor, though that may just be me ;)) is how easy it is to connect. I actually just got some wire from the local hardware store, plugged pieces of it into the controller connector, and then attac…
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#29a Minecraft clone in hardware means all code is hardware?
The assembly language for this chip will be redstone :)