Linus Torvalds on AVX512

Post by kzrdude » Sun, Jul 12, 2020, 9:15 AM UTC

superjan wrote: post #13

throwaway_pdp09 wrote: post #9

The very wide AVX stuff with integer ops, like these from wiki: - AVX-512 Byte and Word Instructions (BW) – extends AVX-512 to cover 8-bit and 16-bit integer operations[3] - AVX-512 Integer Fused Multiply Add (IFMA) - fused multiply add of integers using 52-bit precision. could be very useful. I could have done with those recently. They also don't (AFAIK) cause cpu scaling (polite term for downclocking). He may well…

52 bit precision? typo?

Post by throwaway_pdp09 » Sun, Jul 12, 2020, 9:16 AM UTC

gridlockd wrote: post #19

abainbridge wrote: post #12

What are the forces in chip design that are at play here? Over the last 10-15 years, fabs have continued to fit more and more logic gates per unit area, but haven't reduced the power consumption per gate as much. As a result, if you fill your modern chip with compute gates, you cannot use them all at once because the chip will melt. Or at least you can't have them all running at max clock rates. One solution is to in…

AVX is not a "special purpose block", it's Intel's answer to not adding special purpose blocks on customer demand, like you can do with ARM. Crypto or video decoding comes to mind, those would be much faster with dedicated silicon, but more general AVX instructions can get you halfway there. Well, maybe a quarter. People point out that AVX uses a lot of power, but they ignore that the same algorithm running instead o…

Post by jfkebwjsbx » Sun, Jul 12, 2020, 9:17 AM UTC

RantyDave wrote: post #2

Are Intel just delaying the inevitable? Is it safe to say (even today) that a slow GPU will crunch big matrices faster than a fast CPU? And that's before we get to price/performance. So all that's left is the bottleneck around PCIe which, in theory, leaves the CPU with an advantage only for small datasets - which we don't really care about anyway (because they happen quickly). Maybe the tradeoff is somewhere interest…

Post by throwaway_pdp09 » Sun, Jul 12, 2020, 9:20 AM UTC

gridlockd wrote: post #15

throwaway_pdp09 wrote: post #9

The very wide AVX stuff with integer ops, like these from wiki: - AVX-512 Byte and Word Instructions (BW) – extends AVX-512 to cover 8-bit and 16-bit integer operations[3] - AVX-512 Integer Fused Multiply Add (IFMA) - fused multiply add of integers using 52-bit precision. could be very useful. I could have done with those recently. They also don't (AFAIK) cause cpu scaling (polite term for downclocking). He may well…

If he was right with FP, he'd know better than the business analysts at Intel. Instead, his opinion is based on what the market looked like thirty years ago. Nine years ago, AMD tested the hypothesis that really more "cores" and higher integer throughput were all that was needed and that FP performance didn't matter. The resulting architecture (Bulldozer) was a near-fatal disaster. It didn't even work out in the data…

Post by tails4e » Sun, Jul 12, 2020, 9:25 AM UTC

abainbridge wrote: post #12

What are the forces in chip design that are at play here? Over the last 10-15 years, fabs have continued to fit more and more logic gates per unit area, but haven't reduced the power consumption per gate as much. As a result, if you fill your modern chip with compute gates, you cannot use them all at once because the chip will melt. Or at least you can't have them all running at max clock rates. One solution is to in…