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Using SDRAM in FPGA Designs

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Re: Using SDRAM in FPGA Designs

#21

Post by tverbeure »

lnsru wrote: post #20
dormando wrote: post #12

Earlier quoted context omitted.

They make those too. HyperRAM is pretty popular for small FPGA projects: https://www.mouser.com/new/issi/issi-hyperram/ - there are tradeoffs in potential performance/interface/usability/etc but you end up saving a lot of LUT's and troubleshooting time.

Is there free and functional controller for HyperRAM available? In theory this type of memory is nice, but with no free IP block for this memory, it is a show stopper.

Here you go: https://github.com/blackmesalabs/hyperram

The controller is really not very complex, so it shouldn't be a showstopper.

Re: Using SDRAM in FPGA Designs

#22

Post by robomartin »

SDRAM control is fairly simple to implement almost right from the state diagrams. Squeezing performance out of the chips is a different matter.

Looking at my own controller code from about 15 years ago, you need a 34 state one-hot state machine and the rest comes right out of the diagram and data sheets. Careful placement and layout (I'm talking both about within the FPGA and on the PCB) does the rest. For example, for best performance you want some of the flip-flops located right at the IOB's.

Still, it's cool that something like this is available for those who, for whatever reason, might choose not to undertake writing their own. Nice.

Re: Using SDRAM in FPGA Designs

#23

Post by leetbulb »

This is very interesting and well put together. The diagrams are great. Very easy to read and understand as a software developer that rarely interacts with such low level things. Likely because you're also a software developer :)

I'm curious about introducing a phase shifted clock with a PLL in order to get the rise/fall timings correct. Is that standard in other controller implementations? Is that technique something that's used in other, similar situations? It sounds like a pretty generic and simple way to solve timing issues of that nature. I guess I'm mostly wondering how you came up with that solution and if there are any alternatives? The minds of EE people intrigue me :)

Re: Using SDRAM in FPGA Designs

#24

Post by jlokier »

leetbulb wrote: post #23

This is very interesting and well put together. The diagrams are great. Very easy to read and understand as a software developer that rarely interacts with such low level things. Likely because you're also a software developer :) I'm curious about introducing a phase shifted clock with a PLL in order to get the rise/fall timings correct. Is that standard in other controller implementations? Is that technique somethin…

If you like that, you'll love "wave pipelining", where the information ripples across a circuit with different sub-cycle phases at different positions in the circuit.

Re: Using SDRAM in FPGA Designs

#25

Post by fargle »

Awesome job. I particularly like the size of the code. When I see that state diagram, or think about what you have to do to control DRAM, or look at other COTS and OpenSource controller cores, I always was super leery of the complexity. This is very tight and clean!

Looks like you used wavedrom for timing diagrams. What did you use to make the state diagrams?

Re: Using SDRAM in FPGA Designs

#26

Post by panpanna »

This is very well written and the code looks very clean!

It's a bit verbose, but mostly because he makes everything parametrized so you can easily customize it for different targets.

There are only two things I don't like: he is calling some registers latches and he is mixing std_logic_vector and unsigned in the interface.

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