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FRAM is far from trillions of cycles, more close to billions, which still kills it after ~5-7 years of intense use.
That's more than flash. That's more that an SSD, even, probably. If you're writing to flash or FeRAM that much it seems to me that You're Doing It Wrong.
It's great stuff, but still low capacity and high cost in commercial chips. If you want to play with it, check out TI's MSP430FRxxxx microcontrollers. They have FRAM instead of Flash. Also, there are 8-pin FRAM chips with the same pinouts as generic QSPI Flash/RAM/etc chips which you can buy today. Again, it's still low-density and expensive, but that seems to be improving and it's fun to make applications which can…
And destructive reads with limited life cycles, assures a steady recurring revenue for TI...
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FRAM is far from trillions of cycles, more close to billions, which still kills it after ~5-7 years of intense use.
No, FRAM really is in the trillions of RW cycles. https://www.cypress.com/file/209146/download
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FRAM is far from trillions of cycles, more close to billions, which still kills it after ~5-7 years of intense use.
What microcontroller will see continued and "Intense" use of it's internal flash? The worst I do to mine is to log sensor data in absence of wifi, that's in the order of bits/minute.
TI's spec for 10^10 endurance is for random writes
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No, FRAM really is in the trillions of RW cycles. https://www.cypress.com/file/209146/download
TI spec for FRAM is 10^10, but in real life you do feel that it's noticeably lower.
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What microcontroller will see continued and "Intense" use of it's internal flash? The worst I do to mine is to log sensor data in absence of wifi, that's in the order of bits/minute.
Due to destructive reads, any XIP read ends up in a write. And the most grievous case is when your function code ends up just few bits longer than cache. That means that those few bytes will get hammered, individually, every cycle. TI's spec for 10^10 endurance is for random writes
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Unless you lose power in the interim. Flash doesn't have that problem, and normal RAM has it so badly that we rely on Flash to store permanent data and only use DRAM as an ephemeral cache.
The first datasheet I found for a Cypress FRAM chip gives a required power down rate of at most 30us/V which allows it to continue to provide normal operation protecting data. It's a very easy limitation to live with and engineers often deal with far more difficult problems in unexpected power loss than this.
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Unless you lose power in the interim. Flash doesn't have that problem, and normal RAM has it so badly that we rely on Flash to store permanent data and only use DRAM as an ephemeral cache.
Because dram loses its memory when powered off not because there's some issue with how refresh works. Needing to refresh memory after a read is hardly any engineering challenge. We've been dealing with it since memory's inception.