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The Dark Silicon Problem and What It Means for CPU Designers (2013)

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Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#21

Post by namibj »

a_wild_dandan wrote: post #15
Phillipharryt wrote: post #7

From the article "The heat generation per unit area of an integrated circuit passed the surface of a 100-watt light bulb in the mid 1990s, and now is somewhere between the inside of a nuclear reactor and the surface of a star. " I can't tell if this is hyperbole or not, it amazes me but no amount of googling is coming up with a useful answer. Is anyone able to confirm or deny it for me?

(Intensity) = (Power) / (Unit Area) (Sun's Radius) = 695 x 10^6 m (Sun's Power) = 4 x 10^26 W (CPU Output) = 75 W (Die Size) = 37 mm x 37 mm (Sun Intensity) = (4 x 10^26 W ) / (4 x pi x (695 x 10^6 m)^2) ~ 66 x 10^6 (CPU Intensity) = (75 W) / (0.0014 m^2) ~ 53 x 10^3 I'm getting a several orders of magnitude higher W/m output for the sun. Perhaps I made an algebra mistake?

Yes. You can handle 100W on a 300mm^2 chip. Or 300W on a large one, compare AMD Ryzen/ Nvidia Volta (MXM/V100).

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#22

Post by tormeh »

deepnotderp wrote: post #19
blackflame7000 wrote: post #2

Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall. Seems to me more internal volume might allow for more cleaver head distribution channels

1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance* 2. Power delivery is now ~n times worse where n is your transistor layer count. * 3. Connections between chips are very slow, power hungry and expensive. Fabrication of "monolithic" 3D is temperature wise painful and usually results in crummier transistors. With that being said, innov…

The heat can be tackled in part by pumping water through holes in the CPU. I believe it was IBM that came up with this. Can't tell if it's feasible or not.

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#23

Post by blackflame7000 »

jacquesm wrote: post #13
woah wrote: post #5

Earlier quoted context omitted.

I think op is talking about 6 flat normal chips as the sides. This would allow for cooling stuff inside the cube. Maybe having only 5 of the sides as chips would make it even easier to have a heat sink. The center of the cube could be copper or something.

You can't cool from the inside of that cube without having some way of transporting the heat out of it. All you'd end up doing is heating that inside up to the temperature of the dies and after that there would be no more cooling effect (and this would happen in a few seconds after starting the whole thing up). You could do an 'inverse' of this by cooling the dies from the outside and having the interconnects in the…

What if you used electronic cooling to chill a copper thermal conductor?

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#24

Post by jonhendry18 »

jacquesm wrote: post #13
woah wrote: post #5

Earlier quoted context omitted.

I think op is talking about 6 flat normal chips as the sides. This would allow for cooling stuff inside the cube. Maybe having only 5 of the sides as chips would make it even easier to have a heat sink. The center of the cube could be copper or something.

You can't cool from the inside of that cube without having some way of transporting the heat out of it. All you'd end up doing is heating that inside up to the temperature of the dies and after that there would be no more cooling effect (and this would happen in a few seconds after starting the whole thing up). You could do an 'inverse' of this by cooling the dies from the outside and having the interconnects in the…

I think woah means that the top would be open. So instead of a cube it'd be an open box. A heat sink (or arrangement of peltier coolers attached to a fan and heat sink, or whatever) would fit down into the box and be in contact with the five core-containing sides.

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#25

Post by perl4ever »

andlier wrote: post #9
Phillipharryt wrote: post #7

From the article "The heat generation per unit area of an integrated circuit passed the surface of a 100-watt light bulb in the mid 1990s, and now is somewhere between the inside of a nuclear reactor and the surface of a star. " I can't tell if this is hyperbole or not, it amazes me but no amount of googling is coming up with a useful answer. Is anyone able to confirm or deny it for me?

After a quick napkin calculation+google it seems the sun has around 20kW of power per square centimeter. So not entirely unfeasible that a cooler star, or a nuclear reactor is closer to the typical 10-100W/cm2 of a modern cpu/gpu. Still some orders of magnitude off from our closest star. (Hope calculation is correct)

Looking at the wikipedia page on red dwarf stars[1], it appears a small star (M9V) might have 8% of the sun's radius and 0.015% of its luminosity. Thus, it would have about 156 times less area, and 2.3% of the output per area of the sun. So taking your figure as given, that means it would be less than 500W / cm^2.

[1]https://en.wikipedia.org/wiki/Red_dwarf

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#26

Post by blackflame7000 »

tormeh wrote: post #22
deepnotderp wrote: post #19

Earlier quoted context omitted.

1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance* 2. Power delivery is now ~n times worse where n is your transistor layer count. * 3. Connections between chips are very slow, power hungry and expensive. Fabrication of "monolithic" 3D is temperature wise painful and usually results in crummier transistors. With that being said, innov…

The heat can be tackled in part by pumping water through holes in the CPU. I believe it was IBM that came up with this. Can't tell if it's feasible or not.

I was thinking by either creating a temperature differential on a copper conductor to chill the cube from within or that the motherboard/walls would provide cooling from the pin side.

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#27

Post by blackflame7000 »

gameswithgo wrote: post #4
blackflame7000 wrote: post #2

Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall. Seems to me more internal volume might allow for more cleaver head distribution channels

less surface area per transistor makes the heat problem worse. they are already a little bit 3d though.

What if the cooling came from the pin side of the chip? Then the surface area is the same

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#28

Post by perl4ever »

wongarsu wrote: post #18
blackflame7000 wrote: post #2

Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall. Seems to me more internal volume might allow for more cleaver head distribution channels

For heat dissipation you want the most surface area per volume (because you can only transfer heat away in the surface area). The optimal arrangement for that would be a huge, flat, one atom thick surface. Another goal we have is low latency (and high clock rate, which is depenend on low latency), which suggests putting everything in a qube or even a shere. So we compromise somewhere in the middle with a square with…

"For heat dissipation you want the most surface area per volume (because you can only transfer heat away in the surface area). The optimal arrangement for that would be a huge, flat, one atom thick surface."

Made me think of this:

https://en.wikipedia.org/wiki/Menger_sponge

Say we have roughly 300 sq mm, that's about 17.32 mm square, which is 8.24e+7 silicon atoms (0.21 nm) across.

Then we have a surface area of roughly 1.36e+16 atoms - the area x 2.

If we make a fractal sponge down to the limit of single atoms, then that's about 16.5 cycles of removing cubes from a 17.32 mm cube. Let's ignore the difficulty of doing it half a time. According to the formulas from wikipedia, the result has a volume of about 0.7% of the original, with 2.4e28 "sides" of atoms exposed.

So the third dimension gets you about 1.8 million times the surface area. I suppose this isn't nearly as good as 4e10 flat sheets with 1 atom separation between each, but you could argue it's more practical because everything is connected...

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#29

Post by deepnotderp »

tormeh wrote: post #22
deepnotderp wrote: post #19

Earlier quoted context omitted.

1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance* 2. Power delivery is now ~n times worse where n is your transistor layer count. * 3. Connections between chips are very slow, power hungry and expensive. Fabrication of "monolithic" 3D is temperature wise painful and usually results in crummier transistors. With that being said, innov…

The heat can be tackled in part by pumping water through holes in the CPU. I believe it was IBM that came up with this. Can't tell if it's feasible or not.

Yes but microfluidics limits how thin each die can be.

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#30

Post by throwwit »

wongarsu wrote: post #18
blackflame7000 wrote: post #2

Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall. Seems to me more internal volume might allow for more cleaver head distribution channels

For heat dissipation you want the most surface area per volume (because you can only transfer heat away in the surface area). The optimal arrangement for that would be a huge, flat, one atom thick surface. Another goal we have is low latency (and high clock rate, which is depenend on low latency), which suggests putting everything in a qube or even a shere. So we compromise somewhere in the middle with a square with…

I think a dimpled fabrication would be best... with whatever amounts to heat sinks on both sides.
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