GRVI Phalanx joins The Kilocore Club • Hacker News Board

Re: GRVI Phalanx joins The Kilocore Club

#21

Post by jsgray » Sat, Jan 21, 2017, 1:55 PM UTC

quickben wrote: post #2

If I'm not mistaken, the devices go for 5-6k for the eval kit?

The board used (VCU118) is $7000.

As noted the Digilent Arty is $99 and hosts up to 32 cores. The XC7020 Zynq devices should host 80. That includes the Zedboard, the original Parallella kickstarter ed., the forthcoming Snickerdoodle Black (?), and the Digilent Pynq which is $65 Q1 for students. It is my intention to put out a version of GRVI Phalanx for 7020s, at least a bitstream and SDK, perhaps more, but much to do. Note the 7 series (including XC7A35T of Arty and the XC7Z020) have BRAMs but not UltraRAMs so those clusters have 4K instruction RAMs and 32K shared cluster RAMs. The 4-8K/128K clusters possiblr om the new UltraScale+ devices afford more breathing room for code and data per cluster.

Re: GRVI Phalanx joins The Kilocore Club

#22

Post by nickpsecurity » Sat, Jan 21, 2017, 3:28 PM UTC

jsgray wrote: post #20

nickpsecurity wrote: post #11

Earlier quoted context omitted.

Can't the tools do it relatively fast with a geometric method if the individual cores already have area/timing data to use and are homogenous? And a FPGA instead of an ASIC? My reading the various papers on synthesis as a non-hardware guy made me think this job shouldn't be as hard on that as the SOC's whose components vary considerably in individual attributes.

I wish it were so. While it is straightforward to do regular placement at the block level or even at the individual LUT/slice level using RPMs (relationally placed macros) or absolute LOC placement of LUTs in the XDC implementation constraints file, most of the implementation time goes into routing and there is not an easy mainstream way to take a routed one tile design and step and repeat it (say) 210 times across t…

That makes sense. Thanks.

Re: GRVI Phalanx joins The Kilocore Club

#23

Post by aseipp » Sat, Jan 21, 2017, 3:49 PM UTC

gamiecc wrote: post #10

duskwuff wrote: post #8

Earlier quoted context omitted.

Better for FPGA development. The FPGA on the Arty is slightly larger (28K -> 33K logic cells), and all peripherals, including memory, are connected directly to the FPGA instead of through the ARM SoC. Also, the I/O headers are omitted from the $99 Parallela board, so it's difficult to program. (No JTAG connector.)

does it means that it is possible to done the 1680 cores thing on the Arty board? if can't, what made the Xilinx board more suitable to implement the 1680-cores on it ?

Both of them are Xilinx boards. One of them is just a really, really high end xilinx board, so it basically has enough programmable fabric to hold 1680 cores. The other is cheap and can't hold as many cores.