Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

IBM debuts sub-1 nanometer chip technology

newsroom.ibm.com

Post reply on HN
Print view View original

191–200 of 217 posts

Re: IBM debuts sub-1 nanometer chip technology

#191

Post by meindnoch »

adrian_b wrote: post #59
buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

As it can be seen from the photos, horizontally the features are much bigger than 5 nm. For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm. The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary. The vertical thicknesses of various layers may be of only a few nanomet…

>The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer

We should flip the transistors sideways then!

Re: IBM debuts sub-1 nanometer chip technology

#192

Post by jhide »

YetAnotherNick wrote: post #184
u1hcw9nx wrote: post #85

Earlier quoted context omitted.

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Why is density any bit important? All I care about is the price per transistor, and the power usage(mostly gate charge and leakage current?).

Why is that all you care about? Stepping down a node gets you dramatically improved timing and design feasibility. The reduced density means you can pack the same design into less area. Your most challenging timing paths now have to traverse a shorter distance, and you can fit more of them relative to certain node-size invariant structures

Re: IBM debuts sub-1 nanometer chip technology

#193

Post by nazgulsenpai »

rvba wrote: post #176
BitwiseFool wrote: post #66

Earlier quoted context omitted.

>"The electron wave function will simply just appear wherever it wants (within the electron probability cloud)." I don't know which is more ridiculous, the fact that reality works like this, or, that a species of apes was able to figure this out.

I find it ridiculoua that we believe it is random probability instead of trying to find (and maybe later mitigate) the real sources of this randomness.

There's a whole branch of theoretical physics dedicated to this.

Re: IBM debuts sub-1 nanometer chip technology

#194

Post by jingpostmedia »

topspin wrote: post #53
ac29 wrote: post #31

Earlier quoted context omitted.

> IBM no longer owns any fabs Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space" I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability

It's a lab. It's where ASML brings up the prototype machine and gets it working, with IBM talent working out the problems and getting it ready for commercial operation. They won't make chips at scale there: the facility isn't designed for that part. The thing to understand here is that isn't a simple, clean, comprehensible business arrangement. The Albany facility is highly subsidized by the state. IBM has their hook…

[flagged]

Re: IBM debuts sub-1 nanometer chip technology

#195

Post by u1hcw9nx »

YetAnotherNick wrote: post #184
u1hcw9nx wrote: post #85

Earlier quoted context omitted.

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Why is density any bit important? All I care about is the price per transistor, and the power usage(mostly gate charge and leakage current?).

[flagged]

Re: IBM debuts sub-1 nanometer chip technology

#196

Post by tancop »

rswail wrote: post #190
HerbManic wrote: post #160

Earlier quoted context omitted.

This is why I suspect we will be neat the upper limits of this around the late 2030's. We are just running too close to the fundamental limits. And so far there isn't anything really radical even on the horizon as a solution for this.

Aren't we reaching the point where there is no "solution" in terms of density and physical dimensions? It's like the speed of light being a constant, or the Planck length being the smallest that can be subject to standard physics. Quantum computing, which is a complete change in the actual physical model of computing, appears to be the only alternative.

all production ics have a flat layout with 3d transistors. the physical limit is how close can the features on one wafer get before theres too much tunneling.

there is a clear way forward with wafer stacking instead of shrinking layouts but so far we only have amd v-cache style asymmetric designs with memory stacked on top of compute. for a fully connected stack that acts like a single chip you need insane precision to align the wafers and a way to remove heat from the middle so the chips dont fry themselves.

if someone finds a way to stack cpu cores without thermal issues that will be a real revolution. huawei might be close with their logic folding but nobody knows if it really works and what the heat problems are like.

Re: IBM debuts sub-1 nanometer chip technology

#198

Post by sylware »

adrian_b wrote: post #59
buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

As it can be seen from the photos, horizontally the features are much bigger than 5 nm. For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm. The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary. The vertical thicknesses of various layers may be of only a few nanomet…

Marketing scams has been the norm for the silicon industry for a big decade.

How would you fix that? This is a global scam. Big Markets regulating them: that would have to be the USA and EU.

Re: IBM debuts sub-1 nanometer chip technology

#200

Post by sbergot »

YetAnotherNick wrote: post #184
u1hcw9nx wrote: post #85

Earlier quoted context omitted.

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Why is density any bit important? All I care about is the price per transistor, and the power usage(mostly gate charge and leakage current?).

isn't density a way to lower both the price and energy dissipation (so better heat management & energy efficiency)?
Post reply on HN