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Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

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Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#191

Post by antifa »

sangnoir wrote: post #177
cyberpunk wrote: post #120

Earlier quoted context omitted.

If someone asked to keep my change I would say no too. Why the fsck? Is it normal to beg during work where you’re from?

> Is it normal to beg during work where you’re from? Yes - but they call it tipping 'round these parts. They even have prominently displayed tip jars and everything.

Wait staff at restaurant asking "would you like change?" is normal.

Gas station clerk asking "can I keep your change?" is so random and unexpected it makes the story confusing.

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#192

Post by antifa »

colechristensen wrote: post #158
pdnell wrote: post #148

Earlier quoted context omitted.

Yet they’ll buy their own quarry or glass factory…

Because it's cheaper...

Raises are usually cheaper than recruiting, also raises are cheaper than quarries...

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#193

Post by ksec »

MBCook wrote: post #44

Thanks to being based on their phone chips Apple came out of the gate with the M1 and cleaned everyone’s clock on performance-per-watt while putting in good to great numbers in general (as a CPU). But their rate of improvement on the A series has been slowing on general tasks. They’re on the same process node, and only increased frequency a bit. Is it really that surprising that performance didn’t take a massive jump…

>So why here?

99.999999% of internet comments on M2, or even anything hardware related are pretty much junk. Anandtech used to do some explanation into these sort of things, but as it turns out people aren't interested in in-depth analysis, they just want benchmarks. You end up having them drifting towards mass / mainstream media or LinusTechTip type of content. RealWorldTech doesn't do any these anymore, partly because there is very little money to be made on the consumer side of things. You have other site which talks about Semiconductor Engineering and Business type of content. Unfortunately every time they were posted on HN, no one has shown any interest or complaining about how the content looks too "Enteprisy or Cooperate" because they were intended for B2B settings.

It also isn't just consumers or enthusiast. When viewed from the outside most people would have expected programmers, or what they now called Software Engineers to have some sort of High Level understanding on hardware. But most developers, especially Web Developers, are so abstracted from hardware they dont know or do not care about it.

Broadly speaking this isn't just with hardware, but also every other subject.

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#194

Post by ksec »

sushicat wrote: post #58
GeekyBear wrote: post #55

From Anandtech's deep dive into the performance and efficiency cores in the A15, which are reused here in the M2. Performance Cores: >Apple A15 performance cores are extremely impressive here – usually increases in performance always come with some sort of deficit in efficiency, or at least flat efficiency. Apple here instead has managed to reduce power whilst increasing performance, meaning energy efficiency is impr…

This is a really great article from Anandtech with benchmarks and analysis, it explained a lot of things. > The overall performance gains are quite disappointing when you factor in the raw cost increase that comes with this new M2 and the fact that it has been nearly 2 years since the M1’s introduction. Also the logic of article in the title is little weird to me. M1 was introduced in the same year as A14, they use t…

>Though I'm curious why Apple didn't use A16's core in M2.

We will know soon enough. My guess is that A16 is designed with TSMC 3nm in mind, that is why ( rumour ) only the new iPhone Pro will get A16, and iPhone 14 will stick to A15.

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#195

Post by ksec »

dhanna wrote: post #5
daguava wrote: post #2

There's a lot of claims of poached talent in the article, basically claiming [paraphrasing] "Apple, maintaining their stressful work env and not paying to shore that up lost some rockstars" How true is this? If they're on the money it's an excellent example of a talent retention miss leading to a demonstrable mediocrity in delivery.

The youngest, strongest RTL engineer I know jumped from Apple to Rivos.

>Rivos

[1], I hope that is not him.

[1] https://www.reuters.com/legal/litigation/apple-lawsuit-says-...

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#196

Post by ksec »

drawingthesun wrote: post #34

A few comments here about how Apple is losing a lot of top talent to rival Rivos, a stealth startup. What would Rivos business model be? I’m genuinely interested seems interesting to me. Would they be positioning themselves as the next Qualcomm? Or perhaps sell a superior chip to Apple at some point?

>What would Rivos business model be? Would they be positioning themselves as the next Qualcomm?

Realistically speaking, most likely to be ARM, IMG or CEVA type of IP companies.

But since it is RISC-V, and we are on HN, I wont be surprised if some people expect them to give out their design for free.

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#197

Post by epolanski »

yieldcrv wrote: post #176
nickpp wrote: post #130

Earlier quoted context omitted.

When working with money, the rich are also more likely to hit the countless rules and limitations the banking regulations impose on us "for our own good". Just like as a programmer I am going mental when encountering absurd and ineffective account password rules lets say (one special char, one upper case, one non-letter, etc) while a lay person would just sigh and comply.

exactly, on the other side of this, the rich person should have learned how to get better banking service that doesn't encumber them with these fund movement limitations most “anti money laundering” or “security” stuff is actually just that one bank’s poor and inaccurate implementation of a law. most of it is just company policy and nothing related to the law. with electronic funds, the entire banking system relies o…

this has nothing to do with "better banking systems".

There are laws in italy and there are very specific amounts you can use per month before controls have to be triggered.

60k transactions, abroad are 12 times what you can transfer without declaring exactly what is the money from, where is it from. Especially when sending and receiving money to african countries.

Tax evasion and laundering are high in italy and banks easily deny you their services if they smell something.

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#198

Post by epolanski »

antifa wrote: post #190
yieldcrv wrote: post #175

Earlier quoted context omitted.

some banks waive fees for non profits your bank did not one of my biggest pet peeves is how low-level employees cant tell that their organization isn’t doing the normal thing

Wouldn't surprise if the lady did not have a tax id associated with a non profit.

Bingo, she wanted to send 60k to that fresh account and then move it to africa, which raised multiple suspicions.

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#199

Post by ezconnect »

adrr wrote: post #139
ezconnect wrote: post #104

Earlier quoted context omitted.

Getting debt is the only way they could bring their cash home to avoid tax.

Can you explain the process? I can’t make it work to avoid tax. I assume Apple’s debt is credit lines to fund inventory.

Just an example, tax rate 30% and corporate bond rate is 0.7% it's a no brainer choice for them.

Re: Apple M2 Die Shot and Architecture Analysis – Big Cost Increase and A15 Based IP

#200

Post by brigade »

janwas wrote: post #188
inkyoto wrote: post #86

Earlier quoted context omitted.

> Soo... basically a 2x speedup in going from 4x128b to 2x512b ALUs, after discounting the frequency difference. But realistically, Intel's client configurations are 3x256b, which is only 25-40% faster in that paper. 2.4x difference was, in fact, reported, however I still find it somewhat difficult to interpret the reported results. The processing unit size difference alone and the number of LU's can't account for su…

I am that engineer; happy to clarify/go into more detail. First, just to ensure we're on the same page: the speeds we quote are sort goodput, i.e. amount of sorted data produced per time. Memory bus is only incidental to keeping the vector units fed. The key bottleneck is partitioning. AVX-512 does really well there because it has dedicated compressstore instructions, and it's actually even faster to partition a vect…

> (even if they can actually execute all instructions concurrently, which is not clear to me and unlikely - Intel can also only execute some instructions on certain ports)

It's pretty symmetrical, moreso than Cortex-X2's 4 pipelines; there's analysis that on M1 only some floating point and crypto instructions can't execute on all 4 pipelines. [1] (TP in that table is inverse throughput)

Which means that, for example, byte permutes from tables 256b or less can actually achieve the same throughput on M1 as with Intel's AVX-512, since M1 can sustain 4x 2-register TBL per cycle. And doing the exact equivalent of a 512b vpermb (3 cycle latency, 1/cycle throughput) can be done with 5 cycles latency and 0.33/cycle throughput on M1, via 4x 4-register TBL.

Well, a vpermd in NEON would need an extra MLA to convert indexes, and vpermi2* equivalents fall off a cliff. And Intel still has p01 free, and COMPACT is SVE. But in general, a lot of the parallelism that enables AVX-512 implementations will convert directly into ILP across 128b vectors.

> This seems unlikely because we're sorting 8 MB and my understanding is that cores (unless L2==LLC) generally have private, partitioned L2 caches, so 3 MB in the case of M1. Is that incorrect?

Anandtech [2] measured the same L2 latency up to about 8MB single-core, so regardless of the details, 8MB is a pretty significant cliff on M1. Regardless, RAM bandwidth is ~60GB/s, and unlike Intel, can be just about saturated by a single core.

[1] https://dougallj.github.io/applecpu/firestorm-simd.html

[2] https://www.anandtech.com/show/16252/mac-mini-apple-m1-teste...

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