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RISC-V Is Sloooow

marcin.juszkiewicz.com.pl

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Re: RISC-V Is Sloooow

#181

Post by userbinator »

rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

ARM was never a "speed demon"; it started out as a low power small-area core and clearly had more complexity and thought put into it than MIPS or RISC-V.

Over a decade ago: https://news.ycombinator.com/item?id=8235120

RISC-V will get there, eventually.

Strong doubt. Those of us who were around in the 90s might remember how much hype there was with MIPS.

Re: RISC-V Is Sloooow

#182

Post by userbinator »

computably wrote: post #176
sidewndr46 wrote: post #165

Earlier quoted context omitted.

You're correct but I guess my thoughts are if we're going to wind up with a mess of extensions, why not just use x86-64?

> why not just use x86-64? Uh, because you can't? It's not open in any meaningful sense.

The original amd64 came out in 2003. Any patents on the original instruction set have long expired, and even more so for 32-bit x86.

Re: RISC-V Is Sloooow

#183

Post by userbinator »

wk_end wrote: post #173
snvzz wrote: post #169

Earlier quoted context omitted.

There's reason RV32E and RV64E, with half the registers, are a thing. RV32I/RV64I isn't small enough. There are many chips in the market that do embed 8051s for janitorial tasks, because it is small and not legally encumbered. Some chips have several non-exposed tiny embedded CPUs within. RISC-V is replacing many of these, bringing modern tooling. There's even open source designs like SERV that fit in a corner of an…

Per https://en.wikipedia.org/wiki/Transistor_count , even an 8051 has 50K transistors, which reinforces my claim that 26K really doesn't seem like a big ask for an MCU core. Whether that means a barrel shifter is worth it or not is a totally orthogonal question, of course. (Although I do have to eat my words here - I didn't check that Wikipedia page, and it does actually list a ~6K RISC-V core! It's an experimental a…

I don't know if that construction might allow for a more efficient transistor count and it's totally impractical - 1KHz clock speed, 1-bit ALU, etc. - for almost any purpose, but it is technically a RISC-V implementation significantly smaller than 26K

That sounds like a microcoded RISC-V implementation, which can really be done for any ISA at the extreme expense of speed.

Re: RISC-V Is Sloooow

#184

Post by userbinator »

adgjlsfhk1 wrote: post #85
hackyhacky wrote: post #72

Earlier quoted context omitted.

> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Same could be said of MIPS. My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.

the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips

MIPS patents have long expired too (and incidentally for any other CPU released prior to 2006), so that's a moot point.

Re: RISC-V Is Sloooow

#185

Post by direwolf20 »

newpavlov wrote: post #44
rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

In some cases RISC-V ISA spec is definitely the one to blame: 1) https://github.com/llvm/llvm-project/issues/150263 2) https://github.com/llvm/llvm-project/issues/141488 Another example is hard-coded 4 KiB page size which effectively kneecaps ISA when compared against ARM.

The first one is common across many architectures, including ARM, and the second is just LLVM developers not understanding how cmpxchg works

Re: RISC-V Is Sloooow

#186

Post by userbinator »

sitharus wrote: post #129
hackyhacky wrote: post #78

Earlier quoted context omitted.

> On the other hand, detecting integer overflow in software is extremely expensive, increasing both the program size and the execution time considerably, Most languages don't care about integer overflow. Your typical C program will happily wrap around. If I really want to detect overflow, I can do this: add t0, a0, a1 blt t0, a0, overflow Which is one more instruction, which is not great, not terrible.

Because the other commenter wasn’t posting the actual answer, I went to find the documentation about checking for integer overflow and it’s right here https://docs.riscv.org/reference/isa/unpriv/rv32.html#2-1-4-... And what did I find? Yep that code is right from the manual for unsigned integer overflow. For signed addition if you know one of the signs (eg it’s a compile time constant) the manual says addi t0, t1, +i…

Contrast with x86:

    add eax, ecx
    jo overflow

Re: RISC-V Is Sloooow

#187

Post by musicale »

hackyhacky wrote: post #72
adgjlsfhk1 wrote: post #68

Earlier quoted context omitted.

> Also the bit manipulation extension wasn't part of the core. This is primarily because core is primarily a teaching ISA. One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Anything powerful to run (a non built from source manually) linux will support a profile that bundles all the commonly needed inst…

> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Same could be said of MIPS. My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.

As you indicate, MIPS was widely used in computer architecture courses and textbooks, including pre-RISC-V editions of Patterson & Hennessy (Computer Organization & Design) and Harris & Harris (Digital Design and Computer Architecture.

In spite of the currently mediocre RISC-V implementations, RISC-V seems to have more of a future and isn't clouded by ISA IP issues, as you note.

Re: RISC-V Is Sloooow

#188

Post by musicale »

adgjlsfhk1 wrote: post #85
hackyhacky wrote: post #72

Earlier quoted context omitted.

> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Same could be said of MIPS. My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.

the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips

This is largely contradicted by the (pre RISC-V) MIPS editions of Patterson & Hennessy, Harris & Harris, etc., which teach you how to design a MIPS datapath (at the gate level.)

Regarding silicon implementations, consider that 1) you can synthesize it from HDL/RTL designs using modern CAD tools, and 2) MIPS was originally designed to be simple enough for grad students to implement with the primitive CAD tools of the 1980s (basically semi-manual layout).

Re: RISC-V Is Sloooow

#189

Post by userbinator »

api wrote: post #12
rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

A pattern I've noticed for a very long time: A lot of times the path to the highest performing CPU seems to be to optimize for power first , then speed, then repeat. That's because power and heat are a major design constraint that limits speed. I first noticed this way back with the Pentium 4 "Netburst" architecture vs. the smaller x86 cores that became the ancestor of the Core architecture. Intel eventually ran into…

NetBurst was supposed to be the application of RISC principles to x86 taken to its extreme (ultra-long pipelines to reduce clock-to-clock delay, highest clock speed possible --- basically reducing work-per-clock and hoping that reduces complexity enough to increase clock speed to compensate.) The ALU was 16 bits, "double pumped" with the carry split between the two, which lead to 32-bit ALU operations that don't carry between the lower and upper halves actually finishing a clock cycle faster than those with a carry.

https://stackoverflow.com/questions/45066299/was-there-a-p4-...

Re: RISC-V Is Sloooow

#190

Post by throwaway27448 »

primis wrote: post #27
throwaway27448 wrote: post #25

[flagged]

Hey! I get this is a throwaway account so you might not answer, but I really, really don't like opening an article and having the first thing I see in a thread be someone calling the author a slur. There are ways of expressing insult without bringing intellectual disabilities into the mix.

[flagged]
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