Earlier quoted context omitted.
Even rice cookers started doing this by advertising "fuzzy logic".
Fuzzy logic rice cookers are the result of an unrelated fad in 1990s Japanese engineering companies. They added fuzzy controls to everything from cameras to subways to home appliances. It's not part of the current ML fad.
YC is wrong about LLMs for chip design
181–190 of 283 posts
Re: YC is wrong about LLMs for chip design
#182Re: YC is wrong about LLMs for chip design
#183Earlier quoted context omitted.
> 1. Learn how the subject matter experts do the work. This will get harder I think over time as low hanging fruit domains are picked - the barrier will be people not technology. Especially if the moat for that domain/company is the knowledge you are trying to acquire (NOTE: Some industries that's not their moat and using AI to shed more jobs is a win). Most industries that don't have public workings on the internet…
> This will get harder I think over time as low hanging fruit domains are picked - the barrier will be people not technology. Especially if the moat for that domain/company is the knowledge you are trying to acquire (NOTE: Some industries that's not their moat and using AI to shed more jobs is a win). Also consider that there exist quite a lot of subject matter experts who simply are not AI fanboys - not because they…
After all in a capitalist economy the last to be disrupted generally gets "all the spoils" as purchasing power (and hence prices/wages) move from least scarce/disrupted skills to more scarce skills which allows the last to be disrupted to have more time to accumulate wealth/assets to shield themselves from AI even more.
Re: YC is wrong about LLMs for chip design
#184Earlier quoted context omitted.
I like this reasoning. It is shortsighted to say that LLMs aren’t well-suited to something (because we cannot tell the future) but it is not shortsighted to say that LLMs are well-suited to something (because we cannot tell the future)
I kinda suspect that things that are expressed better with symbols and connections than with text will always be a poor fit to large LANGUAGE models. Turning what is basically a graph into a linear steam of text descriptions to tokenize and jam into an LLM has to be an incredibly inefficient and not very performant way of letting “AI” do magic on your circuits. Ever try to get ChatGPT to play scrabble? Ever try to de…
Re: YC is wrong about LLMs for chip design
#185Nvidia is trying something similar: https://blogs.nvidia.com/blog/llm-semiconductors-chip-nemo/ I'd want to know about the results of these experiments before casting judgement either way. Generative modeling has actual applications in the 3D printing/mechanical industry.
If the evaluation of the approach is "it works great if you train it on a few decades of the best designs from a successful fabless semiconductor company", I would say that if you plan to use that method as a startup, you're clearly going to fail. Nobody's going to give away their crown jewels to train an LLM that designs chips for other companies.
Re: YC is wrong about LLMs for chip design
#186I don’t mind LLMs in the ideation and learning phases, which aren’t reproducible anyway. But I still find it hard to believe engineers of all people are eager to put a slow, expensive, non-deterministic black box right at the core of extremely complex systems that need to be reliable, inspectable, understandable…
Re: YC is wrong about LLMs for chip design
#187Earlier quoted context omitted.
I kinda suspect that things that are expressed better with symbols and connections than with text will always be a poor fit to large LANGUAGE models. Turning what is basically a graph into a linear steam of text descriptions to tokenize and jam into an LLM has to be an incredibly inefficient and not very performant way of letting “AI” do magic on your circuits. Ever try to get ChatGPT to play scrabble? Ever try to de…
There are lots of reasons to doubt the present-day ability of LLMs to help with chip design, but I don't think any of these things above are why. Chip design isn't done with schematics. If an LLM can write Python given enough training data, it can write SystemVerilog given a similar amount of training (though the world currently lacks enough high-quality open source SV to reach an equivalent level.) We can debate whe…
To a nail, every hammer has a purpose.
Re: YC is wrong about LLMs for chip design
#188Earlier quoted context omitted.
I didn't get into this in the article, but one of the major challenges with achieving superhuman performance on Verilog is the lack of high-quality training data. Most professional-quality Verilog is closed source, so LLMs are generally much worse at writing Verilog than, say, Python. And even still, LLMs are pretty bad at Python!
I would imagine it is a reasonably straightforward thing to create a simulator that generates arbitrary chip designs and the corresponding verilog that can be used as training data. It would be much like how AlphaFold was trained. The chip designs don't need to be good, or even useful, they just need to be valid so the LLM can learn the underlying relationships.
Re: YC is wrong about LLMs for chip design
#189Earlier quoted context omitted.
AI still has subhuman performance for art. It feels like the venn diagram of people who are bullish on LLMs and people who don't understand logistic curves is a circle.
You ask 100,000 humans each to make a photo realistic rendering of a alpaca playing basketball on the moon in 90 seconds, an LLM is going to outperform every single one of them.
Also, they might not be able to do it. eg most models can't generate "horse riding an astronaut" or "upside-down car".
Re: YC is wrong about LLMs for chip design
#190Earlier quoted context omitted.
If feels like the entire world has gone crazy. Even the serious idea that the article thinks could work is throwing the unreliable LLMs at verification ! If there's any place you can use something that doesn't work most of the time, I guess it's there.
Only if it fails in the same way. LLMs and the multi-agent approach operate under the assumption that they are programmable agents and each agent is more of a trade off against failure modes. If you can string them together, and if the output is easily verified, it can be a great fit for the problem.