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DRAM has a design flaw from 1966. I bypassed it [video]

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Re: DRAM has a design flaw from 1966. I bypassed it [video]

#171
post #164
post #156

Earlier quoted context omitted.

I can google, thanks. My point is that nobody is buying mainframes with redundant memory to avoid refresh stalls. It’s a mostly irrelevant freebie on hardware you bought for fault tolerance.

Do you have evidence that this is a fact? Have you looked at the computing requirements documents for, for example, stock exchanges? I have it on good evidence that stock exchanges ran on mainframes. They are essentially the counterparty (in a computing sense not a financial sense) in each placed order. If someone is willing to run a fiberoptic cable from Chicago to New York or New Jersey to exploit reduced propagati…

The low latency matching engines in colos run Linux these days, and we use microwave instead of fiber. Incoming orders are processed by hardware receive timestamp, so predicting jitter doesn’t give you an advantage. Clearing and settlement I’m not sure about, not latency critical though, mainframes wouldn’t surprise me there.

Re: DRAM has a design flaw from 1966. I bypassed it [video]

#172
post #6

Love the format, and super cool to see a benchmark that so clearly shows DRAM refresh stalls, especially avoiding them via reverse engineering the channel layout! Ran it on my 9950X3D machine with dual-channel DDR5 and saw clear spikes from 70ns to 330ns every 15us or so. The hedging technique is a cool demo too, but I’m not sure it’s practical. At a high level it’s a bit contradictory; trying to reduce the tail late…

Another point about HFT - They're mostly using FPGAs (some use custom silicon) which means that they have much tighter control over how DRAM is accessed and how the memory controller is configured. They could implement this in hardware if they really need to, but it wouldn't be at the OS level.

Not really. FPGAs run some simple proven strategies, but hardware guys can't keep up with how fast quants iterate on new strategies - so CPUs stay relevant.

Re: DRAM has a design flaw from 1966. I bypassed it [video]

#173
In effect if the operating system knew about the DRAM layout, it could for instance double critical data structures and race the processing. Maybe this would be helpful in the networking areas.

On the other hand this can maybe get fixed in hardware by just copying the page that's being refreshed to the side somewhere, eliminating the whole waiting problem. Last but not least, AFAIK writes to a row already recharge the capacitors so there shouldn't be a need to refresh it. What am I missing?

Re: DRAM has a design flaw from 1966. I bypassed it [video]

#174

Earlier quoted context omitted.

This is a 54 minute video. I watched about 3 minutes and it seemed like some potentially interesting info wrapped in useless visuals. I thought about downloading and reading the transcript (that's faster than watching videos), but it seems to me that it's another video that would be much better as a blog post. Could someone summarize in a sentence or two? Yes we know about the refresh interval. What is the bypass? Up…

Unnecessarily negative imo. I like the video because I cant read a blog post in the background while doing other stuff, and I like Gadget Hackwrench narrating semi-obscure CS topics lol

You're saying that the audio channel of that video has the useful information all by itself. The video channel, which consumes most of the bandwidth, is useless. You could go a little further and say about 80% of the 54 minute audio is also useless, and it could be cut to maybe 10 minutes. Keep going and say to post it as text instead of audio, so you can read it in 2 minutes. Now you don't have to put it in the background.
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