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AMD's Turin: 5th Gen EPYC Launched

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Re: AMD's Turin: 5th Gen EPYC Launched

#171

Post by p_l »

kristianp wrote: post #74
formerly_proven wrote: post #70

Earlier quoted context omitted.

Power and PA-RISC shipped servers, though. MAJC on the other hand > Sun built a single model of the MAJC, the two-core MAJC 5200, which was the heart of Sun's XVR-1000 and XVR-4000 workstation graphics boards.

MAJC: https://en.m.wikipedia.org/wiki/MAJC Why have I not heard of those before?

By the time of XVR GPUs Sun was pretty much exiting the workstation market, and unlike Elite3D and Creator3D the competition has widened for "good enough" PC alternatives using Nvidia and similar chips

Re: AMD's Turin: 5th Gen EPYC Launched

#172

Post by ksec »

aurareturn wrote: post #108

Phoronix recently reviewed the 196 core Turin Dense against the AmpereOne 192 core. * Ampere MSRP $5.5K vs $15K for the EPYC. * Turin 196 had 1.6x better performance * Ampere had 1.2x better energy consumption In terms of actual $/perf, Ampere 192 core is 1.7x better than Turin Dense 196 core based on Phoronix's review. So for $5.5k, you can either buy an AmpereOne 192 core CPU (274w) or a Turin Dense 48 core CPU (30…

Ampere's MSRP is pretty close to most system vendor is paying. You could expect most vendor buy EPYC or Xeon at close to 50% off MSRP.

Re: AMD's Turin: 5th Gen EPYC Launched

#173

Post by Remnant44 »

menaerus wrote: post #166
unnah wrote: post #161

Earlier quoted context omitted.

A Zen 5 core has four parallel AVX-512 execution units, so it should be able to execute 128 16-bit operations in parallel, or over 24k on 192 cores. However I think the 192-core processors use the compact variant core Zen 5c, and I'm not sure if Zen 5c is quite as capable as the full Zen 5 core.

Right, I found this interesting as a thought exercise and took it from another angle. Since it takes 4 cycles to execute FMA on double-precision 64-bit floats (VFMADD132PD) this translates to 1.25G ops/s (GFLOPS/s) per each core@5GHz. At 192 cores this is 240 GFLOPS/s. For a single FMA unit. At 2x FMA units per core this becomes 480 GFLOPS/s. For 16-bit operations this becomes 1920 GFLOPS/s or 1.92 TFLOPS/s for FMA w…

The execution units are fully pipelined, so although the latency is four cycles, you can receive one result every cycle from each of the execution units.

For a Zen 5 core, that means 16 double precision FMAs per cycle using AVX 512, so 80gflop per core at 5ghz, or twice that using fp32

Re: AMD's Turin: 5th Gen EPYC Launched

#174

Post by menaerus »

Remnant44 wrote: post #173
menaerus wrote: post #166

Earlier quoted context omitted.

Right, I found this interesting as a thought exercise and took it from another angle. Since it takes 4 cycles to execute FMA on double-precision 64-bit floats (VFMADD132PD) this translates to 1.25G ops/s (GFLOPS/s) per each core@5GHz. At 192 cores this is 240 GFLOPS/s. For a single FMA unit. At 2x FMA units per core this becomes 480 GFLOPS/s. For 16-bit operations this becomes 1920 GFLOPS/s or 1.92 TFLOPS/s for FMA w…

The execution units are fully pipelined, so although the latency is four cycles, you can receive one result every cycle from each of the execution units. For a Zen 5 core, that means 16 double precision FMAs per cycle using AVX 512, so 80gflop per core at 5ghz, or twice that using fp32

You're absolutely right, not sure why I dumbed down my example to a single instruction. Correct way to estimate this number is to feed and keep the whole pipeline busy.

This is actually a bit crazy when you stop and think about it. Nowadays CPUs are packing more and more cores per die at somewhat increasing clock frequencies so they are actually coming quite close to the GPUs.

I mean, top of the line Nvidia H100 can sustain ~30 to ~60 TFLOPS whereas Zen 5 with 192 cores can do only half as much, ~15 to ~30 TFLOPS. This is not even a 10x difference.

Re: AMD's Turin: 5th Gen EPYC Launched

#175

Post by Remnant44 »

menaerus wrote: post #174
Remnant44 wrote: post #173

Earlier quoted context omitted.

The execution units are fully pipelined, so although the latency is four cycles, you can receive one result every cycle from each of the execution units. For a Zen 5 core, that means 16 double precision FMAs per cycle using AVX 512, so 80gflop per core at 5ghz, or twice that using fp32

You're absolutely right, not sure why I dumbed down my example to a single instruction. Correct way to estimate this number is to feed and keep the whole pipeline busy. This is actually a bit crazy when you stop and think about it. Nowadays CPUs are packing more and more cores per die at somewhat increasing clock frequencies so they are actually coming quite close to the GPUs. I mean, top of the line Nvidia H100 can…

I agree! I think people are used to comparing to a single threaded execution of non-vectorized code, which is using .1% of a modern CPU's compute power.

Where the balance slants all the way towards gpus again is the tensor units using reduced precision...

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