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DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

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Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#171

Post by sroussey »

Aerroon wrote: post #170
verall wrote: post #99

Earlier quoted context omitted.

This is a bad comparison. DRAM margins are razor thin and unlike transistors, DRAM has not gotten much smaller, which is the main cost savings gained from process improvements. Instead, server and accelerator vendors want ever faster and higher performance DRAM, and so these performance gains trickle down to consumers, but nothing is driving price down. People on here literally think Moore's is a natural law and if c…

> DRAM margins are razor thin and unlike transistors, DRAM has not gotten much smaller, which is the main cost savings gained from process improvements. Should we then expect SRAM to eventually be cheaper than DRAM?

You might see larger in-processor or on-module memory (in a chiplet design). Lots of factors to deal with.

Have those numbers been growing? Don’t have data on hand myself.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#172

Post by NelsonMinar »

DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

One of the great ironies of modern computers is we dispensed with ECC just as we started ballooning out the size of RAM and shrinking the transistors so that single bit errors were more likely. I'd be very grateful for system ECC.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#173

Post by pedrocr »

Taniwha wrote: post #169
pedrocr wrote: post #98

Earlier quoted context omitted.

So AMD is back to having a northbridge again but it's on the same package instead of the motherboard for latency reasons? Or could we actually get away with a northbridge on the motherboard again?

Sort of - it allows them to build lots of different sorts of systems - many CPU chiplets and a mem controller, 1 CPU and a mem controller etc etc all from the same basic components - Intel have to spin a new chip for each SKU, AMD can build different SKUs by packaging stuff differently - it gives them a lot more flexibility and means they can spin out new stuff to fit a new market segment much more quickly

I know that motivation but I'm more curious about the hardware architecture angle. Integrating the memory controller in the CPU was supposedly a big gain at the time. Now it's in a different chip and multi-socket motherboards already have to traverse the board to access RAM attached to another chip. Are the interconnects better now and so going back to a single northbridge is workable? Would it simplify the topology in multi-socket systems to have all the RAM together instead of having to take care with process affinity to RAM? I'd love a source for discussion around these kinds of tradeoffs.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#175

Post by sroussey »

klodolph wrote: post #153
verall wrote: post #140

Earlier quoted context omitted.

> The thing that's gotten smaller is the minimum feature size on a silicon wafer. No, even minimum feature size is improving much slower than in the past. Fabs are focusing on specifics that are still giving gain: lower power transistors, SRAM. Really high performance transistors like for amps have not gotten much smaller, DRAM has not gotten much smaller, analog has not gotten much smaller. The capacitors and sense…

That’s a very satisfying answer. I’m aware that the processes for logic, flash, and DRAM have some significant differences but I don’t know much more than “differences exist” (e.g. and therefore you have a different die for CPU and flash). My reasoning is, at best, “SSDs have gotten cheaper, SSDs are kind of like RAM, shouldn’t RAM get cheaper?” and I know that’s not exactly an expert opinion.

SSDs are non-volatile — they don’t need power and constant refreshing like DRAM does. So you can do different things based on a different heat and power budget, like going 3D and adding more layers that would kill regular ram or a cpu, etc.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#176

Post by wmf »

klodolph wrote: post #153
verall wrote: post #140

Earlier quoted context omitted.

> The thing that's gotten smaller is the minimum feature size on a silicon wafer. No, even minimum feature size is improving much slower than in the past. Fabs are focusing on specifics that are still giving gain: lower power transistors, SRAM. Really high performance transistors like for amps have not gotten much smaller, DRAM has not gotten much smaller, analog has not gotten much smaller. The capacitors and sense…

That’s a very satisfying answer. I’m aware that the processes for logic, flash, and DRAM have some significant differences but I don’t know much more than “differences exist” (e.g. and therefore you have a different die for CPU and flash). My reasoning is, at best, “SSDs have gotten cheaper, SSDs are kind of like RAM, shouldn’t RAM get cheaper?” and I know that’s not exactly an expert opinion.

NAND flash went from one layer to 128 layers over the last decade while DRAM is still one layer.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#177

Post by Freaky »

DCKing wrote: post #115
kasabali wrote: post #88

Earlier quoted context omitted.

What I read around is that's not the enterprise ECC, it's more akin to ECC bits used in flash memory. It'll allow manufacturers to play fast and loose with memory.

I guess what I don't understand then is what big advantage "enterprise ECC" has left over this DDR5 "non-enterprise ECC". (Seriously, why is ECC "enterprise"? Everybody wins with memory error correction.) If regular DDR5 can correct single bitflips, it is on par in correction capabilities with "enterprise ECC" DDR4. Maybe this won't allow for the detection of multiple flips, and maybe won't even report single bit fli…

> I guess what I don't understand then is what big advantage "enterprise ECC" has left over this DDR5 "non-enterprise ECC"

ECC should be end-to-end, so it detects and (hopefully) corrects errors anywhere along the path, not just within a chip.

Step 1 of handling a lot of ECC correction events is to reseat the DIMM, because often it's just an issue with the connection, not actually a memory defect.

And you may not care too much about reports of correction events, but you definitely want to see correction failures reported - the point is, after all, to avoid corruption.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#178

Post by rosege »

gambiting wrote: post #44
Spooks wrote: post #7

Earlier quoted context omitted.

I like to grab RAM towards the end of the generation, so far it has been the best bang for my buck (for my personal computer). From the production estimates, looks like I'll jump into DDR5 at the end of 2023 or most likely 2024

Yeah, when DDR4 came out first, the early modules were easily outperformed by good DDR3 modules on every metric except power consumption. DDR5 will be king in a few years.

It will be interesting to see if history repeats. I'm holding off buying a new PC until this is known.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#179

Post by cogman10 »

filereaper wrote: post #139

To my hardware colleagues on HN, what prevents something similar to Dennard Scaling on DRAMs? My very naive textbook knowledge is that every bit for DRAM uses up a single transistor and a capacitor, whereas a SRAM cell uses up 6 transistors. How is it then that with all the scaling so far that traditional SRAMs haven't caught up with DRAM capacities? A single DRAM chip is huge compared to the total die size of any mi…

There are 2 things to keep in mind.

First, DRAM and SRAM are more than just the transistors, they are the lines going into each of the transistors carrying the signal. They are also all the control circuitry around those transistors. When you write out, you aren't just involving the 6 transistors to store, but rather a whole host of control transistors.

Next up, changes in current on a wire induce current on surrounding lines. This induced current is results in what's known as "cross talk". There are a bunch of methods to combat this, the primary one is to make sure there is enough space between lines to avoid it. This means that while your transistor size may get smaller and smaller, you still have a limit on how close you can place those transistors, otherwise you risk unwanted bit flips. DRAM has a major advantage here simply because it requires fewer lines to control state. That results in a more dense packing of memory.

With those two points in mind, there's simply no way for SRAM to ever have the same price/GB or density as DRAM (without the market screwing with prices).

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#180

Post by jtl999 »

lucb1e wrote: post #143
DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

I actually tried really hard to get RAM to corrupt a bit for a school project and didn't manage a single bit flip. How often have you actually heard of data corruption due to non-ECC memory? Either yourself, any degree of 'friend of a friend', or perhaps a study that looked into the matter with more success than I had. I don't mean a newspaper story because exceptional cases are reported because they're rare exceptio…

I was able to to induce single and multi bit errors into DDR4 RAM by increasing the clock frequency, reducing timings, and undervolting.
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