Earlier quoted context omitted.
Or time to have Kernel live on dedicated cache not ever accessed/shared with anything else. Let the CPU speculate all it wants, just not when playing in the kernel's cache. It may even be time for dedicated kernel cpus/cores.
Reading Kernel memory (Meltdown attack) is extra bad but regular user processes being able to read each other's memory (Spectre attack) is also very bad and not solvable by isolating the kernel.
LLVM patch to fix half of Spectre attack
171–180 of 248 posts
Re: LLVM patch to fix half of Spectre attack
#172Earlier quoted context omitted.
Or time to have Kernel live on dedicated cache not ever accessed/shared with anything else. Let the CPU speculate all it wants, just not when playing in the kernel's cache. It may even be time for dedicated kernel cpus/cores.
Reading Kernel memory (Meltdown attack) is extra bad but regular user processes being able to read each other's memory (Spectre attack) is also very bad and not solvable by isolating the kernel.
Re: LLVM patch to fix half of Spectre attack
#173Earlier quoted context omitted.
Isn't that a bit like a firefighter saying your house burning down is "glorious"?
How many firefighters do you know? I guarantee you every one of them gets excited at the prospect of a "good" structure fire.
Re: LLVM patch to fix half of Spectre attack
#174Re: LLVM patch to fix half of Spectre attack
#175Earlier quoted context omitted.
An indirect jump is when your program asks the CPU to transfer control to a location that your code itself computes: "jmp %register". Compare to a direct jump, where the destination of the jump is hardcoded into the jump instruction itself: "jmp $0x100". Most programs have indirect jumps somewhere. Higher-level languages with virtual function calls have lots of indirect jumps, because they parameterize functions: to…
Pretty well, thanks. What I'm wondering is: The attack is using the data fetched into the cache from a speculative indirect jump to do a timing attack and discover what's in the former, correct? Why can't the CPU mark the cache area it fetched in the speculative jump as "stale" and discard it? Why wouldn't that fix the problem?
Re: LLVM patch to fix half of Spectre attack
#176Earlier quoted context omitted.
The 50% was for a microbenchmark of C++ code making heavy use of virtual. V-tables and jump tables get much more expensive. Any execution path that is known at compile time is not affected.
I wonder where that leaves Java, C#, Node.js etc. Do the VMs generate code that suffers from this?
Would be interesting how it balances out in total.
Re: LLVM patch to fix half of Spectre attack
#177I, for one, am eternally grateful for the incredibly bright people who take the time to patch this sort of stuff.
Re: LLVM patch to fix half of Spectre attack
#178Earlier quoted context omitted.
It's not just "untrusted code" any more. The "true secure" way is not running any untrusted code, not connecting to any untrusted networks, and not accepting or storing any untrusted data. At that point you can't run a computer. It's just not an answer to say "don't let bad things in" because bad things are always going to get in. And with side channel exploits getting more and more common, and with them being worse…
Eliminating out of order execution completely would result in much more than a 15% performance reduction.
Re: LLVM patch to fix half of Spectre attack
#179Earlier quoted context omitted.
tptacek exploits computers for a living, so it's glorious for him :)
It's not that it makes the practice of breaking into computers that much more interesting so much as it makes the underlying field much more interesting to work in. The engineering problems just got a lot more complex. We're all taking an attack vector seriously --- microarchitectural side channels --- that we weren't taking as seriously before, except as an abstract threat to crypto and a way of defeating a mitigati…
Re: LLVM patch to fix half of Spectre attack
#180RISC-V impact? With all the reports of these attacks, I have not seen mention of risc-v. Since they are in the process of finalizing a lot of specs including memory model and privileged instructions, I wonder if there will be last minute changes to mitigate these vulnerabilities.
RISC-V is an ISA, so it depends on the implementation.
>> While makeshift processor-specific countermeasures are possible in some cases, sound solutions will require fixes to processor designs as well as updates to instruc- tion set architectures (ISAs) to give hardware architects and software developers a common understanding as to what computation state CPU implementations are (and are not) permitted to leak.