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DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

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Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#161

Post by Retric »

formerly_proven wrote: post #62
Retric wrote: post #14

Earlier quoted context omitted.

Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.

Is that so? I don't think it is. Core-to-RAM latency is in the neighborhood of 50 ns (well-tuned Intel system with low-latency memory) to ~80 ns (bottom-of-the-barrel system). At propagation speed, that's about 10 meters. A big chunk of this latency is internal to the CPU (so is not influenced by distance to the memory at all), another big chunk is the inherent slowness of accessing a DRAM array (10+ ns, independent…

10 meters one way = 5 meters round trip. Trace the longest physical path a signal travels from your CPU to a memory chip on the DIMM and back, it’s likely longer than you think. And yea on it’s own plenty of overhead, but everyone making latency tradeoffs bashing their design as part of a larger system with a single unavoidable limit.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#162

Post by wmf »

filereaper wrote: post #139

To my hardware colleagues on HN, what prevents something similar to Dennard Scaling on DRAMs? My very naive textbook knowledge is that every bit for DRAM uses up a single transistor and a capacitor, whereas a SRAM cell uses up 6 transistors. How is it then that with all the scaling so far that traditional SRAMs haven't caught up with DRAM capacities? A single DRAM chip is huge compared to the total die size of any mi…

DRAM has followed Dennard scaling but that has slowed just as it has for logic. https://semiengineering.com/1xnm-dram-challenges/

I don't know why you would expect a 6T SRAM cell to ever be smaller than a 1T DRAM cell given that both of them are scaling. Also, DRAM die sizes appear to be 40-80 sq. mm which is smaller than processors. https://www.semiconductor-digest.com/2019/09/13/dram-nand-an...

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#163

Post by ip26 »

DCKing wrote: post #115
kasabali wrote: post #88

Earlier quoted context omitted.

What I read around is that's not the enterprise ECC, it's more akin to ECC bits used in flash memory. It'll allow manufacturers to play fast and loose with memory.

I guess what I don't understand then is what big advantage "enterprise ECC" has left over this DDR5 "non-enterprise ECC". (Seriously, why is ECC "enterprise"? Everybody wins with memory error correction.) If regular DDR5 can correct single bitflips, it is on par in correction capabilities with "enterprise ECC" DDR4. Maybe this won't allow for the detection of multiple flips, and maybe won't even report single bit fli…

I don't know what "enterprise ECC" means, but there are certainly grades of protection, from single bit error detection (parity) thru triple error correct quadruple error detect, and inline vs non-inline correction schemes. (for the latter, the machine has to stop, go back, fix the error, & resume, potentially at significant performance cost)

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#164

Post by fgonzag »

johnchristopher wrote: post #70
GGfpc wrote: post #28

Earlier quoted context omitted.

The PS5 can play PS4 games so it would be a worse financial decision I guess

Is it full automatic, pixel perfect compatibility or only a bunch of games are ?

Should be, at the end of the day they are both just X86_64 systems. It isn't like the console generations of old where each one would used a specialized CPU usually designed specifically for that console. (The PS3 had to include a full PS2 chip for its compatibility layer)

All that said, I do see them somehow screwing it up.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#165

Post by nn3 »

verall wrote: post #99
varispeed wrote: post #83

Earlier quoted context omitted.

It is easy. For example you could hire 10000 people to perform calculations for your complex mathematical model (like it was done century ago) or you can buy Raspberry PI to perform the same task in no time. Which will be cheaper?

This is a bad comparison. DRAM margins are razor thin and unlike transistors, DRAM has not gotten much smaller, which is the main cost savings gained from process improvements. Instead, server and accelerator vendors want ever faster and higher performance DRAM, and so these performance gains trickle down to consumers, but nothing is driving price down. People on here literally think Moore's is a natural law and if c…

I call it the economic fallacy. It's very common, especially on discussion forums like this.

Every problem is only related to how much competition there is, but not to how hard the underlying problem is.

It's somewhat related to the "awareness fallacy": The belief that every problem that humanity has can be solved if just everyone is aware and willing to act.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#166

Post by wickedsickeune »

aresant wrote: post #111

Does anybody have a recommendation for a benchmarking suite that in app shows where your bottlenecks are? eg as simple as CPU utilization, GPU utilization, RAM speed utilization?

Benchmarking of what? Based on the task, you need a specific benchmark. If it's gaming, there are various benchmarks, run them, see utilization, whichever is not 100% is the bottleneck.

If it's computation, it's more complicated to discover the bottleneck (your problem may be cache misses, memory bandwidth, architecture that doesn't go well with the algorithm).

Point is, you need to specify the task.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#167

Post by im3w1l »

lucb1e wrote: post #143
DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

I actually tried really hard to get RAM to corrupt a bit for a school project and didn't manage a single bit flip. How often have you actually heard of data corruption due to non-ECC memory? Either yourself, any degree of 'friend of a friend', or perhaps a study that looked into the matter with more success than I had. I don't mean a newspaper story because exceptional cases are reported because they're rare exceptio…

Did you try overclocking your system?

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#168

Post by x87678r »

ksec wrote: post #71

The unanswered question is, will it be cheaper? Price / GB of DRAM hasn't actually fallen much in the 10 years of progression.[1] LPDDR is still over $3/GB. UDIMM is still ~$3 /GB, which is about the same in 2010 / 2011. i.e Despite what you may heard about DRAM price collapse in 2019, the price floor of DRAM has been pretty much the same over the past 10 years. Every other silicon has gotten cheaper, NAND, ICs, just…

That chart is from https://thememoryguy.com/dram-prices-hit-historic-low/ and has some good commentary and other time scales.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#169

Post by Taniwha »

pedrocr wrote: post #98
formerly_proven wrote: post #65

Earlier quoted context omitted.

Intel desktop CPUs are monolithic. A 10900K is a single die, meanwhile a AMD 3900X is three dies: two compute dies and one I/O die (which are sourced from two manufacturers on two different processes afaik). An AMD server CPU has the same compute dies, except more of them, and a very different IO die. The AMD compute dies are only connected to the IO die and other compute dies (and power). All IO connections exclusiv…

So AMD is back to having a northbridge again but it's on the same package instead of the motherboard for latency reasons? Or could we actually get away with a northbridge on the motherboard again?

Sort of - it allows them to build lots of different sorts of systems - many CPU chiplets and a mem controller, 1 CPU and a mem controller etc etc all from the same basic components - Intel have to spin a new chip for each SKU, AMD can build different SKUs by packaging stuff differently - it gives them a lot more flexibility and means they can spin out new stuff to fit a new market segment much more quickly

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#170

Post by Aerroon »

verall wrote: post #99
varispeed wrote: post #83

Earlier quoted context omitted.

It is easy. For example you could hire 10000 people to perform calculations for your complex mathematical model (like it was done century ago) or you can buy Raspberry PI to perform the same task in no time. Which will be cheaper?

This is a bad comparison. DRAM margins are razor thin and unlike transistors, DRAM has not gotten much smaller, which is the main cost savings gained from process improvements. Instead, server and accelerator vendors want ever faster and higher performance DRAM, and so these performance gains trickle down to consumers, but nothing is driving price down. People on here literally think Moore's is a natural law and if c…

>DRAM margins are razor thin and unlike transistors, DRAM has not gotten much smaller, which is the main cost savings gained from process improvements.

Should we then expect SRAM to eventually be cheaper than DRAM?

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