Newbie question: What do verilog and VHDL compile down to, i.e. what is the assembly/machine language for FPGAs?
Developer Preview – EC2 Instances with Programmable Hardware
161–170 of 212 posts
Re: Developer Preview – EC2 Instances with Programmable Hardware
#162Earlier quoted context omitted.
Yes this is cool if you're already using FPGAs and yeah, there will be a market for FPGA designers. But I also think this is FPGAs for the Rest of Us . Suddenly, FPGAs are available without having to buy some development board from Xilinx, install a toolchain, use said (shitty) toolchain ... Me, I was thinking of FPGAs as being something I'd use down the road a few years, eventually, etc. But instead, I'm looking at…
I think this is going to be well outside the pricing range for most people to use for an extended period of time, which is necessary for learning a lot. Depends on the specs of the developer AMI, too, which comes with Vivado and everything. But synthesis can be insanely CPU intensive for large designs, so who knows how they'll spec it. It might cost more due to including a Vivado license. And you'll need to do extens…
You would think after 20+ years of FPGAs, commercial FPGA tools would be more usable and more productive than something a couple guys hacked together from reverse-engineering a small FPGA. But that hasn't been my (limited) experience. Hats off to the IceStorm team.
Re: Developer Preview – EC2 Instances with Programmable Hardware
#163If anyone is wondering how the FPGA board looks like https://imgur.com/a/wUTIp
Good lord that is beautiful. What a massive FPGA.
Re: Developer Preview – EC2 Instances with Programmable Hardware
#164I'm not totally up to date on it, but the RISC-V project has a tool (Chisel) that "compiles" to verilog... Interesting times for sure!
Also checkout clash-lang.org which takes an almost Haskell language to VHDL or Verilog or others.
Re: Developer Preview – EC2 Instances with Programmable Hardware
#165Oh man...this is freaking awesome!
Re: Developer Preview – EC2 Instances with Programmable Hardware
#166Newbie question: What do verilog and VHDL compile down to, i.e. what is the assembly/machine language for FPGAs?
logic-gate layout?
Re: Developer Preview – EC2 Instances with Programmable Hardware
#167These FPGAs are absolutely _massive_ (in terms of available resources). AWS isn't messing around. To put things into practical perspective my company sells an FPGA based solution that applies our video enhancement technology in real-time to any video streams up to 1080p60 (our consumer product handles HDMI in and out). It's a world class algorithm with complex calculations, generating 3D information and saliency maps…
What can each one of those 2.5 million "logic elements" do? Last time I used an FPGA, they were mostly made up of 4-bit LUTs.
How many NOT operations can this do per cycle (and per second)? I realise FPGAs aren't the most suited for this, but the raw number is useful when thinking about how much better the FPGA is compared to a GPU for simple ops.
Re: Developer Preview – EC2 Instances with Programmable Hardware
#168If you don't click through to read about this: you can write an FPGA image in verilog/VHDL and upload it... and then run it. To me that seems like magic. HDK here: https://github.com/aws/aws-fpga (I work for AWS)
How do FPGAs compare with GPUs for the inference stage of Deep Learning algorithms? Can they accelerate it a lot?
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Re: Developer Preview – EC2 Instances with Programmable Hardware
#169These FPGAs are absolutely _massive_ (in terms of available resources). AWS isn't messing around. To put things into practical perspective my company sells an FPGA based solution that applies our video enhancement technology in real-time to any video streams up to 1080p60 (our consumer product handles HDMI in and out). It's a world class algorithm with complex calculations, generating 3D information and saliency maps…
What can each one of those 2.5 million "logic elements" do? Last time I used an FPGA, they were mostly made up of 4-bit LUTs. How many NOT operations can this do per cycle (and per second)? I realise FPGAs aren't the most suited for this, but the raw number is useful when thinking about how much better the FPGA is compared to a GPU for simple ops.
The 2.5 million number quoted in the article is "System Logic Cells", not Logic Elements. Near as I can tell, since I haven't kept pace with Xilinx since their 7 series, a "System Logic Cell" is some strange fabricated metric which is arrived at by taking the number of LUTs in the device and multiplying by ~2. In other words, there is no such thing as a System Logic Cell, it's just a translucent number.
Anyway, the FPGAs being used here are, I believe, based on a 6-LUT (6 input, 2 output). So you'd get about 1.25 million 6-LUTs to work with, and some combination of MUXes, flip-flops, distributed RAM, block RAM, DSP blocks, etc.
Supposing Xilinx isn't doing any trickery and you really can use all those LUTs freely, then you'd be able to cram ~2.5 million binary NOTs into the thing (2 NOTs per LUT, since they're two output LUTs). So 2.5 million NOTs per cycle. I don't know what speed it'd run at for such a simple operation. Their mid-range 7 series FPGAs were able to do 32-bit additions plus a little extra logic, at ~450 MHz and consume 16 LUTs for each adder.
Re: Developer Preview – EC2 Instances with Programmable Hardware
#170If you don't click through to read about this: you can write an FPGA image in verilog/VHDL and upload it... and then run it. To me that seems like magic. HDK here: https://github.com/aws/aws-fpga (I work for AWS)
How do FPGAs compare with GPUs for the inference stage of Deep Learning algorithms? Can they accelerate it a lot?
No, but they do use less power:
To the best of our knowledge, state-of-the-art performance for forward propagation of CNNs on FPGAs was achieved by a team at Microsoft. Ovtcharov et al. have reported a throughput of 134 images/second on the ImageNet 1K dataset [28], which amounts to roughly 3x the throughput of the next closest competitor, while operating at 25 W on a Stratix V D5 [30]. This performance is projected to increase by using top-of-the-line FPGAs, with an estimated through- put of roughly 233 images/second while consuming roughly the same power on an Arria 10 GX1150. This is com- pared to high-performing GPU implementations (Caffe + cuDNN), which achieve 500-824 images/second, while con- suming 235 W. Interestingly, this was achieved using Micros oft- designed FPGA boards and servers, an experimental project which integrates FPGAs into datacenter applications.