I don't understand why the fpga chip vendors don't sell direct to customers. You typically have to go through a distributor, and that entails quite a bit of markup. It doesn't lend itself to the hobby market like raspberry pi for example.
FPGAs Need a New Future
151–160 of 170 posts
Re: FPGAs Need a New Future
#152Earlier quoted context omitted.
My rule of thumb is a 40x silicon area ratio between FPGA and ASIC, a clock speed that is around 5x lower. And a lot more power consumption. If you have an application that can be done on a CPU, with lots of sequences dependencies (such as video compression/decompression), an FPGA doesn’t stand a chance compared to adding dedicated silicon area. That’s even more so if you’d embed an FPGA on a CPU die. Intel tried it…
I have yet to see the "FPGA is less power efficient" thing to be true. People are always comparing the same circuit in an FPGA Vs an ASIC but this is a nonsensical comparison because of three reasons: FPGAs have hard wired blocks like DSPs which do not have any power disadvantages vs "ASIC" (only advantages actually) the likelihood that there is an ASIC that happens to implement your particular design is very low and…
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Re: FPGAs Need a New Future
#153The problem is that FPGA companies don't see themselves as chip companies. They see themselves as CAD software companies. The chip is just a copy-protection dongle.
Pushing 20 years in industry and this is the best take I’ve heard
Re: FPGAs Need a New Future
#154I program FPGAs professionally (Xilinx Zynq, VHDL). I agree that the tool's GUI is atrocious, the actual way to use it is to write everything in TCL scripts, and invoke the tools through a Makefile. I only open the GUI to look at timing issues or ask it for code templates. I disagree with "HDL is software" though. It's not, it's even in the name: "hardware description language". Yes it's a text file with what looks a…
LabVIEW FPGA was amazing, I did all kinds of things with it on the compactRIO controller FPGA
You can write very neat and tidy code with dataflow diagram languages. I did it professionally for years, and there were many others who did as well.
Same thing as any other language, you have to come up ways to organize the code into functions and classes that make sense. Vomiting everything into the top level diagram is the same as 10000 line of code while(1)
You could always tell the exact level of proficiency someone had with LabVIEW immediately when opening the diagram.
The dataflow model maps very well to FPGAs IMO, it's a shame it never became widespread. There was much potential there
Re: FPGAs Need a New Future
#155Neat, but we've been in the same situation for a while. A couple years back, I wrote a tutorial for using an open source stack with the Nandland Go FPGA board: a simple Lattice board. This was because the FPGA book I bought from No Starch required Windows (shock and horror). This was 2023. Now we're coming up into 2026?
Re: FPGAs Need a New Future
#156One big issue with FPGAs is how annoying it is to learn how to use them. I did a course on embedded systems a few years ago and nobody could truly get to enjoy it because we spent most of our time downloading and installing huge toolchains, waiting for synthesis and PnR to complete and debugging weird IDE issues. We need to open up the space to allow people to develop better solutions than what these companies are fo…
Have you seen the YoWASP toolchain for VSCode [1]? It sounds pretty similar.
Re: FPGAs Need a New Future
#157Earlier quoted context omitted.
The main advantage to VHDL is the style of thinking it enforces. If you write your Verilog or SystemVerilog like it's VHDL, everything works great. If you write your VHDL like it's Verilog, you'll get piles of synthesis errors... and many of them will be real problems. So if you learn VHDL first, you'll be on a solid footing.
I haven't learned Verilog, only VHDL and even that with the explicit _ff pattern when I need flips flops and I never felt like there is anything difficult about VHDL Is the North American insistence on teaching Verilog what's setting up students for failure since Verilog looks a bit more like a sequential programming language at first glance?
VHDL is based on Ada, so it also inherits from sequential programming models.
Re: FPGAs Need a New Future
#158I don't get the VHDL or Verilog hate. Digital IC design engineers have no problem with them. True, most of the industry moved to SystemVerilog, mainly for simulation and verification reasons.
It's the weirdnesses of FPGAs though. You aren't really designing a gate level circuit at the end. I'm not sure Verilog or VHDL are to blame here. Maybe they aren't fit for purpose to begin with. I hate the toolchains too. They got worse (sluggish, more paid IPs etc) in the last 15 years. IC design tools cost A LOT more (like 2-3 orders of magnitude more) comparatively but they just work at least!
Re: FPGAs Need a New Future
#159The issue with the software team using an FPGA is that software developers generally aren't very good at doing things in parallel. They generally do a poor job in implementing hardware. I previously taught undergraduates VHDL, the software students generally struggles with the dealing with things running in parallel. VHDL and Verilog are used because they are excellent languages to describe hardware. The tools don't…
> software developers generally aren't very good at doing things in parallel If only hardware people would stop stereotyping. Also, do you guys not use use formal tools (BMC etc) now? Who do you think wrote those tools? Heck all the EDA stuff was designed by software people. I just can't with the gatekeeping. (Btw, this frustration isn't just pointed at you. I find this sentiment being parroted allover /r/FPGA on red…
I was very specific in using the word generally. I taught a mixture of computer science and electronic engineering students. About three to four times more electronic students were competent for every computer science student over the years I taught.
It's not a case of just stating computer scientist weren't capable of doing it. They struggled with the parallelism and struggled with the optimisations and placements when you had to make physical connections on chips.
I'm well aware it's mostly going to be computer scientists writing the tools we use.
For those that want FPGAs to take off like the Arduino platform, I agree. I'd love it. However, it isn't the tooling that's holding it back. The reality is it is that cheaper, faster and easier solutions already exist. Why would you use an FPGA?
Re: FPGAs Need a New Future
#160The issue with the software team using an FPGA is that software developers generally aren't very good at doing things in parallel. They generally do a poor job in implementing hardware. I previously taught undergraduates VHDL, the software students generally struggles with the dealing with things running in parallel. VHDL and Verilog are used because they are excellent languages to describe hardware. The tools don't…
> software developers generally aren't very good at doing things in parallel If only hardware people would stop stereotyping. Also, do you guys not use use formal tools (BMC etc) now? Who do you think wrote those tools? Heck all the EDA stuff was designed by software people. I just can't with the gatekeeping. (Btw, this frustration isn't just pointed at you. I find this sentiment being parroted allover /r/FPGA on red…
> EDA stuff was designed by software people.
No - EDA software is built by hardware experts moonlighting as software engineers, which is partly why it is so obtuse.