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DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

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Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#151

Post by pixl97 »

lucb1e wrote: post #143
DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

I actually tried really hard to get RAM to corrupt a bit for a school project and didn't manage a single bit flip. How often have you actually heard of data corruption due to non-ECC memory? Either yourself, any degree of 'friend of a friend', or perhaps a study that looked into the matter with more success than I had. I don't mean a newspaper story because exceptional cases are reported because they're rare exceptio…

I've seen a ton of it in the field. In general the ram stability is so bad that large operating systems fail to boot from corruption, so most of the time it doesn't get to the data corruption phase.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#152

Post by DCKing »

lucb1e wrote: post #143
DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

I actually tried really hard to get RAM to corrupt a bit for a school project and didn't manage a single bit flip. How often have you actually heard of data corruption due to non-ECC memory? Either yourself, any degree of 'friend of a friend', or perhaps a study that looked into the matter with more success than I had. I don't mean a newspaper story because exceptional cases are reported because they're rare exceptio…

I've seen bit flips reported in edac utils on a system with ECC memory. People routinely try to induce memory errors by overclocking their memory (to verify ECC is working). The triggering of bit flips is the very foundation of the Rowhammer attack (yes, I know Rowhammer can circumvent ECC with advanced techniques). Error correcting codes are used in networking environments, CPU caches, hard drives, anywhere but main memory.

Not sure why memory bit flips have the reputation of being such an edge case. It could be that it was an edge case 20 years ago, but it clearly isn't anymore. Computer memory has changed too.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#153

Post by klodolph »

verall wrote: post #140
LeifCarrotson wrote: post #121

Earlier quoted context omitted.

The thing that's gotten smaller is the minimum feature size on a silicon wafer. The same types of etching and doping processes can be used to create many integrated circuits. DRAM chips are integrated circuts that consist of individual transistors and capacitors for each bit, plus the wiring and logic to read, refresh, and write to those bits. They're substantially transistors. It's true that logic, power, analog, fl…

> The thing that's gotten smaller is the minimum feature size on a silicon wafer. No, even minimum feature size is improving much slower than in the past. Fabs are focusing on specifics that are still giving gain: lower power transistors, SRAM. Really high performance transistors like for amps have not gotten much smaller, DRAM has not gotten much smaller, analog has not gotten much smaller. The capacitors and sense…

That’s a very satisfying answer. I’m aware that the processes for logic, flash, and DRAM have some significant differences but I don’t know much more than “differences exist” (e.g. and therefore you have a different die for CPU and flash).

My reasoning is, at best, “SSDs have gotten cheaper, SSDs are kind of like RAM, shouldn’t RAM get cheaper?” and I know that’s not exactly an expert opinion.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#154

Post by [deleted] »

verall wrote: post #140
LeifCarrotson wrote: post #121

Earlier quoted context omitted.

The thing that's gotten smaller is the minimum feature size on a silicon wafer. The same types of etching and doping processes can be used to create many integrated circuits. DRAM chips are integrated circuts that consist of individual transistors and capacitors for each bit, plus the wiring and logic to read, refresh, and write to those bits. They're substantially transistors. It's true that logic, power, analog, fl…

> The thing that's gotten smaller is the minimum feature size on a silicon wafer. No, even minimum feature size is improving much slower than in the past. Fabs are focusing on specifics that are still giving gain: lower power transistors, SRAM. Really high performance transistors like for amps have not gotten much smaller, DRAM has not gotten much smaller, analog has not gotten much smaller. The capacitors and sense…

[deleted]

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#155

Post by [deleted] »

karmakaze wrote: post #61
Retric wrote: post #14

Earlier quoted context omitted.

Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.

It matters but I wouldn't say it's significant for a typical design. A ns is about 12in (30cm) from Grace Hopper's famous wire visual aid.

[deleted]

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#157

Post by [deleted] »

karmakaze wrote: post #61
Retric wrote: post #14

Earlier quoted context omitted.

Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.

It matters but I wouldn't say it's significant for a typical design. A ns is about 12in (30cm) from Grace Hopper's famous wire visual aid.

[deleted]

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#158

Post by throw0101a »

BoppreH wrote: post #150
throw0101a wrote: post #123

Earlier quoted context omitted.

> Ryan Smith in the link above seems to suggest error correction will be done transparently anyway, and it won't reported to the OS. I once heard a rant from someone on how not reporting this to the OS is really bad for diagnosing issues, even soft errors that are auto-healed. (It could have been from Bryan Cantrill, but couldn't say for sure.)

Zebras All the Way Down - Bryan Cantrill, Uptime 2017 http://www.youtube.com/watch?v=fE2KDzZaxvE&t=35m40s

Yup. There's no rant like a Bryan Cantrill rant. :)

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#159

Post by Retric »

karmakaze wrote: post #61
Retric wrote: post #14

Earlier quoted context omitted.

Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.

It matters but I wouldn't say it's significant for a typical design. A ns is about 12in (30cm) from Grace Hopper's famous wire visual aid.

Don’t forget it’s round trip and more than just across the motherboard but also to the edge of chips and across DIMM modules.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#160

Post by throw0101a »

DCKing wrote: post #128
throw0101a wrote: post #123

Earlier quoted context omitted.

> Ryan Smith in the link above seems to suggest error correction will be done transparently anyway, and it won't reported to the OS. I once heard a rant from someone on how not reporting this to the OS is really bad for diagnosing issues, even soft errors that are auto-healed. (It could have been from Bryan Cantrill, but couldn't say for sure.)

I do think that there will still be some people interested in ECC detection and reporting, but that's not really why I'm interested in ECC memory. The dividing line "enterprise = error correction with monitoring / non-enterprise = silent error correction" is much more sensible than "non-enterprise = no error correction at all, good luck" IMO. Isn't the primary reason why people are looking into diagnostics is because…

Yes, I do not run things at a scale that would need that, but I would appreciate at least a toggle to have it available if needed: default=quiet(er) would be fine for most cases.
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