Reminded me how one famous Russian guy ran Atomic Heart on Elbrus 8S. Elbrus has native translator, though, and pretty good one, afaik. Atomic Heart was kinda playable, 15-25 fps.
Elbrus is/was RISC?-V?
Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
141–149 of 149 posts
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#142Earlier quoted context omitted.
Did they specifically analyze doing alignment on a cache line basis?
This would require specifying a cache line size in the ABI, which is a somewhat odd uarch detail to bubble up. While 64-bytes is conventional for large application processors and has been for a long time, I wouldn't want to make it a requirement.
It's definitely worth analyzing though.
See how big of a block you need to get 90% of the compression benefit, etc.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#143Earlier quoted context omitted.
It shifts implementation complexity from hardware onto software. It's not an inherent advantage, but an extra compiler pass is generally cheaper than increased silicon die area, for example. On a slight tangent, from a security perspective, if your silicon is "too clever" in a way that introduces security bugs, you're screwed. On the other hand, software can be patched.
I honestly find the lack of compiler/interpreter complexity disheartening. It often feels like as a community we don't have an interest in making better tools than those we started with. Communicating with the compiler, and generating code with code, and getting information back from the compiler should all be standard things. In general they shouldn't be used, but if we also had better general access to profiling ac…
I usually talk a lot about Oberon, or Limbo, however their designs were constrained by hardware costs of the 1990's, and how much more the alternatives asked for in resources.
We are three decades away from those days, with more than enough hardware to run those systems, only available in universities or companies with very deep pockets.
Yet, the Go culture hasn't updated themselves, or very reluctantly, with the usual mistakes that were already to be seen when 1.0 came out.
And since they hit gold with CNCF projects, pretty much unavoidable for some work.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#144Earlier quoted context omitted.
Instructions can be completed in one clock cycle, which removes a lot of complexity compared to instructions that require multiple clock cycles. Removed complexity means you can fit more stuff into the same amount of silicon, and have it be quicker with less power.
That's not exactly it; quite a few RISC-style instructions require multiple (sometimes many) clock cycles to complete, such as mul/div, floating point math, and branching instructions can often take more than one clock cycle as well, and then once you throw in pipelining, caches, MMUs, atomics... "one clock cycle" doesn't really mean a lot. Especially since more advanced CPUs will ideally retire multiple instructions…
Got it, so it's more about removing microcode.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#145Earlier quoted context omitted.
Put another way, "try to avoid instructions that can't be executed in a single clock cycle, as those introduce silicon complexity".
But that's not even close to true, either, eg any division or memory operation. In practice there's no such thing as "RISC" or "CISC" anymore really, they've all pretty much converged. At best you can say "RISC" now just means that there aren't any mixed load + alu instructions, but those aren't really used in x86 much, either
You've hit the nail on the head. Really, when people complain about CISC vs RISC, they are mostly complaining about two particular things. The first is that x86 processors carry legacy baggage (aka they have had a long history of success that continues to this day) and the second is that x86 has a lot of variable length instructions. After that, most of the complaints are very nit-picky, such as the number of general purpose registers and how they are named.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#146Earlier quoted context omitted.
That's not exactly it; quite a few RISC-style instructions require multiple (sometimes many) clock cycles to complete, such as mul/div, floating point math, and branching instructions can often take more than one clock cycle as well, and then once you throw in pipelining, caches, MMUs, atomics... "one clock cycle" doesn't really mean a lot. Especially since more advanced CPUs will ideally retire multiple instructions…
Got it, so it's more about removing microcode.
The biggest divide is that no more than a single exception can occur in a RISC instruction, but you can have an indefinite number of page faults in something like an x86 rep mov.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#147Earlier quoted context omitted.
But we define the RISC dream as a dream that efficiency, performance and low-cost could be achieved by cores with very small instruction sets?
Not small instruction sets, simplified instruction sets. RISC’s main trick is to reduce the number of addressing modes (eg, no memory indirect instructions) and reduce the number of memory operands per instruction to 0 or 1. Use the instruction encoding space for more registers instead. The surviving CISCs, x86 and z390 are the least CISCy CISCs. The surviving RISCs, arm and power, are the least RISCy RISCs. RISC V i…
More details on how RISCy or CISCy various chips are:
https://userpages.umbc.edu/~vijay/mashey.on.risc.html
Notably x86 is one of the less CISCy CISCs so it looks like there might be a happy medium.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#148I'm not very familiar with the ecosystem, but I have used this on an RPi4 to run some games through wine.
I'm wondering, how's the landscape nowadays. Is this the leading project for x86 compatibility on ARM? With the rising popularity of the architecture for consumer platforms, I'd guess companies like Valve would be interested in investing in these sort of translation layers.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#149Earlier quoted context omitted.
Got it, so it's more about removing microcode.
The biggest divide is that no more than a single exception can occur in a RISC instruction, but you can have an indefinite number of page faults in something like an x86 rep mov.
That's not even true as you can get lots of exceptions for the same instruction. For example a load can all of these and more (but only one will be reported at a time): instruction fetch page fault, load misaligned, and load page fault.
More characteristic are assumptions about side effects (none for integer, and cumulative flags for FP) and number of register file ports needed.