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DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

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Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#141

Post by r1nkgrl »

varispeed wrote: post #119
wmf wrote: post #112

Earlier quoted context omitted.

Computers have never used FPGA memory controllers that are upgradeable to newer DRAM standards so there's really no reason to say that's the "proper" solution. And memory standards overlap for 4-5 years which also happens to be the lifetime of a PC so the price/performance benefit of future-proofing really isn't there.

This kind of proves my point. It doesn't lead to maximisation of profits therefore it is not being developed.

I would agree that it supports your point. Proves it? no.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#142

Post by DCKing »

nine_k wrote: post #135
DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

A number of Celerons 3XXX and 4XXX support ECC. They are intended for storage systems, like a NAS, or industrial electronics.

If you could point me to a The only thing that comes to mind in that category for me is the PC Engines APU2. The APU2 is a very neat piece of kit, don't get me wrong, but it being the only option is not great either.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#143

Post by lucb1e »

DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

I actually tried really hard to get RAM to corrupt a bit for a school project and didn't manage a single bit flip.

How often have you actually heard of data corruption due to non-ECC memory? Either yourself, any degree of 'friend of a friend', or perhaps a study that looked into the matter with more success than I had. I don't mean a newspaper story because exceptional cases are reported because they're rare exceptions rather than common enough that we'd be likely to come across it in our lifetimes.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#144

Post by verall »

filereaper wrote: post #139

To my hardware colleagues on HN, what prevents something similar to Dennard Scaling on DRAMs? My very naive textbook knowledge is that every bit for DRAM uses up a single transistor and a capacitor, whereas a SRAM cell uses up 6 transistors. How is it then that with all the scaling so far that traditional SRAMs haven't caught up with DRAM capacities? A single DRAM chip is huge compared to the total die size of any mi…

SRAMs are catching up, but they are still much less dense, and are normally configured for smaller line sizes and lower latencies than DRAM. DRAM requires sense amplifiers and capacitors which have scaled both scaled slower than transistors.

From a systems perspective, lots of work has gone into hiding DRAM's faults highlighting its strong points, so a system where DRAM is replaced with SRAM will be more expensive but not realize most of the possible benefits without major redesigns of the memory systems.

Intel has some xeons with over 70MB of L3 and also released some eDRAM chips to play around with this idea, but notice they used eDRAM to get 128MB of L4 on a consumer chip - SRAM is still very expensive!

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#145

Post by lucb1e »

zionic wrote: post #52
orliesaurus wrote: post #6

Yeah, but to the casual user like me, that's going to help with load times... go from 2 seconds to 1 second.

Be more excited that ECC is now part of the standard, and without a speed compromise.

Why would you buy ECC RAM, have you ever seen a single bit flip or heard of anyone that did?

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#146

Post by deegles »

lucb1e wrote: post #143
DCKing wrote: post #76

One thing I'd like to understand better about DDR5 is how well the built-in ECC is going to work to improve reliability. DDR5 comes with "chip level ECC" [1] of which the main purpose is to be able to better sell highly complicated memory chips with minor defects. But as a consequence as I understand, it will allow for the correction of single bit memory flips. With regular DDR4 or previous generations, you don't get…

I actually tried really hard to get RAM to corrupt a bit for a school project and didn't manage a single bit flip. How often have you actually heard of data corruption due to non-ECC memory? Either yourself, any degree of 'friend of a friend', or perhaps a study that looked into the matter with more success than I had. I don't mean a newspaper story because exceptional cases are reported because they're rare exceptio…

Bunch of links to papers here: https://stackoverflow.com/questions/2580933/cosmic-rays-what...

e.g. "2009 Google's paper "DRAM Errors in the Wild: A Large-Scale Field Study" says that there can be up to 25000-75000 one-bit FIT per Mbit (failures in time per billion hours), which is equal to 1 - 5 bit errors per hour for 8GB of RAM after my calculations. Paper says the same: "mean correctable error rates of 2000–6000 per GB per year". "

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#149

Post by Yeroc »

deegles wrote: post #146
lucb1e wrote: post #143

Earlier quoted context omitted.

I actually tried really hard to get RAM to corrupt a bit for a school project and didn't manage a single bit flip. How often have you actually heard of data corruption due to non-ECC memory? Either yourself, any degree of 'friend of a friend', or perhaps a study that looked into the matter with more success than I had. I don't mean a newspaper story because exceptional cases are reported because they're rare exceptio…

Bunch of links to papers here: https://stackoverflow.com/questions/2580933/cosmic-rays-what... e.g. "2009 Google's paper "DRAM Errors in the Wild: A Large-Scale Field Study" says that there can be up to 25000-75000 one-bit FIT per Mbit (failures in time per billion hours), which is equal to 1 - 5 bit errors per hour for 8GB of RAM after my calculations. Paper says the same: "mean correctable error rates of 2000–6000…

And there are ways to manipulate RAM access patterns to induce errors as described in the initial Rowhammer attack paper plus later RAMBleed papers. Hopefully this newer DDR version is designed to be resistant to this type of attack.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#150

Post by BoppreH »

throw0101a wrote: post #123
DCKing wrote: post #118

Earlier quoted context omitted.

Ryan Smith in the link above seems to suggest error correction will be done transparently anyway, so it seems like it won't reported to the OS. So it doesn't look like Intel could cripple it even if they wanted to.

> Ryan Smith in the link above seems to suggest error correction will be done transparently anyway, and it won't reported to the OS. I once heard a rant from someone on how not reporting this to the OS is really bad for diagnosing issues, even soft errors that are auto-healed. (It could have been from Bryan Cantrill, but couldn't say for sure.)

Zebras All the Way Down - Bryan Cantrill, Uptime 2017

http://www.youtube.com/watch?v=fE2KDzZaxvE&t=35m40s

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