141–150 of 159 posts
"The first board without GPU is planned for Q4 2020, following with one with PowerVR GPU in 2021.". Ah, how quickly we forgot the GMA500/Poulsobo chip.
https://arstechnica.com/information-technology/2009/12/pouls...
What sort of person describes a board with a closed-source GPU firmware as "Open Source"?
Interesting that the group behind this is Tsinghua-Berkeley Shenzhen Institute, which is sponsored by UC Berkeley as well as a major Chinese university and the Shenzhen government. China is quite interested in RISC-V gaining traction as trade and security barriers rise and they work to build up their domestic technology sector. Going into wild-ass speculation mode, if this board really is affordable, I wonder if it's…
> Going into wild-ass speculation mode, if this board really is affordable, I wonder if it's being subsidized by the Chinese gov't to encourage RISC-V adoption. You might find this[1] meeting with Steven Zhao interesting. Steven Zhao is the guy behind Orange Pi, raspberry pi alternative. Interesting part translated: Steven announces that Orange Pi can buy a good quality WiFi component for $1, that his cards will have…
Also the pricing of low end Pi models is probably very close to BOM cost too.
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The question is why is a charity organization devoted to education using DRM for protectionism rather than taking an approach where knowledge is more freely shared.
It appears the question has been answered and you just didn't like the answer.
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It appears the question has been answered and you just didn't like the answer.
I understand that they don't want other camera vendors to compete with them. What I don't understand is why they would take that stance as a charity, and what I disagree with is the implied argument that it's better for the Raspberry Pi ecosystem if the hardware is closed.
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That the US has gotten TSMC to boycot Huawei is quite recent. The deal for this was probably done before the latest sanctions. TSMC has massive economies of scale and are just very hard for alternatives to compete with.
Do you have an overview or link how that has come to be by any chance?
Promising hardware, though this isn't looking like comparable hardware even to the Raspberry Pi Zero. Only has a quad-core 64-bit RISC-V (RV64GC) processor at 500+ MHz. RAM size not specified. If it was priced in the $5-15 range it would be more or less practical, but higher than that I'd be buying it solely for the architecture novelty.
I'm a little concerned that these RV64GC implementations all end up at about 500-600 MHz. There's plenty of 1.5 GHz ARM processors at 28 nm.
It was pricey at $999 because the chips are from low volume "shuttle run" aka MPW production (probably $300 or $400 each -- would be maybe $10 in volume production) and the board has 8 GB DDR4 2400 and other expensive things such as FMC connector.
But it's well faster than a Pi 3 and I've had 2.5 years of use out of it already...
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One concrete advantage RISCV has is its variable-length SIMD instruction set. The assembly instructions used for SIMD in RISCV can all operate on data sizes that are various powers of 2. All using the same instructions. You could even call it “SIMD with dynamically-sized data”. Right now, x86 needs one set of instructions for each SIMD data size. That’s why we have SSE, AVX, AVX512, etc. This introduces complexity fo…
Arm SVE is also variable data size, and it's already in production on Fujitsu's massive HPC clusters :P
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> That doesn't make sense --- how would the code know how much to increment pointers by, how many times to loop, alignment, etc. ? You ask the hardware. The current vector width is a register that can be set and queried. https://gms.tf/riscv-vector.html
That is interesting... and actually feels a bit CISCy, but this Configuring a grouping of 8 registers for a vector of 16 elements might look like overkill because 128 bit vector registers are sufficient and should be widely available. On the other hand, there might be a CPU with "V" support that just implements - say - 64 bit vector registers where we would need to group 2 registers. Since a grouping thus may be need…
It's just that if your code doesn't need 32 different vector variables then you can step down to, say, 4 variables with 8x longer registers for more efficiency. You need to know how many live variables your code has (which the compiler knows), not how long the registers are.
See also https://www.seeedstudio.com/Sipeed-Maix-Cube-p-4553.html This is RISC-V, with a neural co-processor (runs YOLO), camera, GPIOs, leds etc. For $25. It runs MicroPython out of the box, but someone has Linux booting on the board equivalent. I have one, and there are teething pains but the platform seems pretty capable.
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The Pi Zero is single core at 1GHz so it's not a totally fair comparison. There are plenty of times I wish I had more cores, even if they were half the speed. Compiling anything on the zero is incredibly slow. It also has slower DDR2 RAM and no USB3 (which makes a big difference for many peripherals).
But zero is well.... a zero .... If you don't want to mess with arduino/esp*, but want a price point and size in that range, with full linux support, to connect a thingy to another thingy (eg sensor to web/mqtt), and don't care about additional power use, you take a rpi0. I don't think it was ever meant as a "normal computer" or a "server" (as we use normal-sized RPis for).