Earlier quoted context omitted.
RISC-V is becoming a worldwide interop standard, and a real one, namely royalty free and which will be stable in time once we get all the "now we know" features, and all that at the ISA level (x86_64 and ARM are _NOT_ worldwide royalty free). And don't be mistaken, there is no perfect ISA (it is said "average"), it does not exist, only a set of trade-offs and compromises which will not fit all use-cases perfectly. RI…
RISC-V is already putting the squeeze on ARM in the embedded market. RISC-V is fewer gates at almost every performance level the embedded market is interested in due to having a tighter, non-legacy ISA (there's even the open SERV core which fits RISC-V into an insanely small 2.1KGe). RISC-V likely has a future in mobile devices as it crawls up the performance tree like ARM did. This leaves ARM in a tight squeeze betw…
And QERV, only slightly bigger, yet dramatically faster.