Coming Soon: AWS Graviton2 Processor for AWS

Post by goosehonk » Thu, Dec 05, 2019, 5:56 AM UTC

monocasa wrote: post #89

goosehonk wrote: post #67

Earlier quoted context omitted.

This comment seems kinda slanted. AVX-512 debuted on Xeon because datacenter operators asked for it. It does not “downclock a whole chip”, it gates the core where it is active and there’s not even that penalty on the current generation parts. “10nm” is marketing fluff which has little or nothing to do with actual semiconductor construction. “Chiplet” is also marketing-speak for “wow this memory topology is hard to pr…

> AVX-512 debuted on Xeon because datacenter operators asked for it. It deputed on workstation accelerator cards. > It does not “downclock a whole chip”, it gates the core where it is active and there’s not even that penalty on the current generation parts. It very much could thermally throttle more than the one core. > “10nm” is marketing fluff which has little or nothing to do with actual semiconductor construction…

Post by dehrmann » Thu, Dec 05, 2019, 6:15 AM UTC

derefr wrote: post #7

vorpalhex wrote: post #3

Earlier quoted context omitted.

This is entirely Intel's fault for trying to get fat by choking out the market with a gazillion UPCs and a ton of markup. They exhausted their own food supply.

Intel's gazillion SKUs are really just a few abstract-ideal "optimal product, highest price" makes of processor, binned down into many different "sub-optimal product, lower price" channels. If you collapse the binnings together, they're really only producing ~four CPUs at a time. At least for commercial availability. There's tons of enterprise SKUs just to serve customers like AWS, of course, but that's not to "squee…

Post by jl6 » Thu, Dec 05, 2019, 6:53 AM UTC

dman wrote: post #10

If Intel makes it out of the current soup with its dominance intact it will make for an interesting case study. Think they are facing the perfect storm on multiple fronts. a. The 10nm process fiasco b. Missing the chiplet concept c. ISA fragmentation - AVX512 which was supposed to be the next big thing was server CPU side only till recently and downclocks the entire chip when used making it extremely hard to reason a…

Post by saagarjha » Thu, Dec 05, 2019, 7:14 AM UTC

wmf wrote: post #114

xxpor wrote: post #92

Earlier quoted context omitted.

Except MIPS and the network.

MIPS processors have mostly been replaced by ARM already.

Post by solidasparagus » Thu, Dec 05, 2019, 7:50 AM UTC

shaklee3 wrote: post #126

solidasparagus wrote: post #101

Earlier quoted context omitted.

Uhh source on AVX512 not downclocking on modern CPUs? We benchmarked ML workloads on the newest chips the cloud had to offer and the slowdown was a significant problem because, as the parent comment said, it is very hard to reason about whether the benefits of vectorized ops will outweigh the the reduced clock speed. Sometimes it does and sometimes it does not - which is a major problem when you have to specify instr…

FPGAs are in a tough place. Like OP said, most people writing RTL make asics, or at least an asic that's programmable. The FPGA target market is getting slimmer, since we have programmable Asics, like GPUs and tpus, that are as performant with easier programming. They will still serve a niche market, but the "write c++ and run on an fpga" will likely never take off.