AMD claims Arm ISA doesn't offer efficiency advantage over x86 • Hacker News Board

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#121

Post by gigatexal » Mon, Sep 08, 2025, 9:47 PM UTC

Yizahi wrote: post #93

fluoridation wrote: post #69

Earlier quoted context omitted.

Does anyone actually care at all about frequencies? I care if my task finishes quickly. If it can finish quickly at a low frequency, fine. If the clock runs fast but the task doesn't, how is that a benefit? My understanding is that both Intel and AMD are pushing high clocks not because it's what consumers want, but because it's the only lever they have to pull to get more gains. If this year's CPU is 2% faster than y…

It's only recently when consumer software has become truly multithreaded. Historically there were major issues with that until very recently. Remember Bulldozer fiasco? They bet on the parallel execution more than Intel at the same time, e.g. same price Intel chip was 4 core, while AMD had 8 cores (consumer market). Single thread performance had been the deciding factor for decades. Even today AMDs outlier SKUs with…

But the OS has been able to take advantage of it since mountain lion with grand central dispatch. I could be wrong with the code name. This makes doing parallel things very easy.

But most every OS can.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#122

Post by ac29 » Mon, Sep 08, 2025, 9:49 PM UTC

nottorp wrote: post #16

Irrelevant. There are two entities allowed to make x86_64 chips (and that only because AMD won the 64 bit ISA competition, otherwise there'd be only Intel). They get to choose. The rest will use arm because that's all they have access to. Oh, and x86_64 will be as power efficient as arm when one of the two entities will stop competing on having larger numbers and actually worry about power management. Maybe provide a…

> Oh, and x86_64 will be as power efficient as arm when one of the two entities will stop competing on having larger numbers and actually worry about power management.

Both Intel and AMD provide runtime power control so this is tunable. The last ~10% of performance requires far more than 10% of the power.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#123

Post by Jensson » Mon, Sep 08, 2025, 9:53 PM UTC

gigatexal wrote: post #113

Jensson wrote: post #96

Earlier quoted context omitted.

Basically yeah, if you compare CPU from same fab then its basically the same. Its just Apple buys next gen fabs while AMD and intel has to be on last gen, so the M computers people compare are always one fab gen ahead. It has very little to do with CPU architecture. They do have some cool stuff about their CPU, but the thing most laud them for has to do with fabs.

Man that either hella discounts all the amazing work Apple’s CPU engineers are doing or hyping up what AMD’s have done. Idk

Isn't it you who is hyping up Apple here when you don't even compare the two using similar architecture? Compare a 5nm AMD laptop low power cpu to Apple M1 and the M1 no longer looks that much better at all.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#124

Post by codedokode » Mon, Sep 08, 2025, 9:54 PM UTC

torginus wrote: post #18

exmadscientist wrote: post #2

This is an entirely uncontroversial take among experts in the space. x86 is an old CISC-y hot mess. RISC-V is a new-school hyper-academic hot mess. Recent ARM is actually pretty good. And none of it matters, because the uncore and the fabrication details (in particular, whether things have been tuned to run full speed demon or full power sipper) completely dominate the ISA. In the past x86 didn't dominate in low powe…

I remember reading this Jim Keller interview: https://web.archive.org/web/20210622080634/https://www.anand... Basically the gist of it is that the difference between ARM/x86 mostly boils down to instruction decode, and: - Most instructions end up being simple load/store/conditional branch etc. on both architectures, where there's literally no difference in encoding efficiency - Variable length instruction has pretty…

x86 decoding must be a pain - I vaguely remember that they have trace caches (a cache of decoded micro-operations) to skip decoding in some cases. You probably don't make such caches when decoding is easy.

Also, more complicated decoding and extra caches means longer pipeline, which means more price to pay when a branch is mispredicted (binary search is a festival of branch misprediction for example, and I got 3x acceleration of linear search on small arrays when I switched to the branchless algorithm).

Also I am not a CPU designer, but branch prediction with wide decoder also must be a pain - imagine that while you are loading 16 or 32 bytes from instruction cache, you need to predict the address of next loaded chunk in the same cycle, before you even see what you got from cache.

As for encoding efficiency, I played with little algorithms (like binary search or slab allocator) on godbolt, and RISC-V with compressed instruction generates similar amount of code as x86 - in rare cases, even slightly smaller. So x86 has a complex decoding that doesn't give any noticeable advantages.

x86 also has flags, which add implicit dependencies between instructions, and must make designer's life harder.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#125

Post by addaon » Mon, Sep 08, 2025, 9:57 PM UTC

Jensson wrote: post #96

gigatexal wrote: post #85

Earlier quoted context omitted.

Wait are you saying the diff in perf per watt from apple arm to x86 is purely on fab leading edge ness?

Basically yeah, if you compare CPU from same fab then its basically the same. Its just Apple buys next gen fabs while AMD and intel has to be on last gen, so the M computers people compare are always one fab gen ahead. It has very little to do with CPU architecture. They do have some cool stuff about their CPU, but the thing most laud them for has to do with fabs.

There's another difference -- willingness to actually pay for silicon. The M1 Max is a 432 mm^2 laptop chip built on a 5 nm process. Contrast that to AMD's "high end" Ryzen 7 8845HS at 178 mm^2 on a 4 nm process. Even the M1 Pro at 245 mm^2 is bigger than this. More area means not just more peak performance, but the ability to use wider paths at lower speeds to maintain performance at lower power. 432 mm^2 is friggin' huge for a laptop part, and it's really hard to compete with what that can do on any metric besides price.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#126

Post by codedokode » Mon, Sep 08, 2025, 9:57 PM UTC

newpavlov wrote: post #108

exmadscientist wrote: post #2

This is an entirely uncontroversial take among experts in the space. x86 is an old CISC-y hot mess. RISC-V is a new-school hyper-academic hot mess. Recent ARM is actually pretty good. And none of it matters, because the uncore and the fabrication details (in particular, whether things have been tuned to run full speed demon or full power sipper) completely dominate the ISA. In the past x86 didn't dominate in low powe…

>RISC-V is a new-school hyper-academic hot mess. Yeah... Previously I was a big fan of RISC-V, but after I had to dig slightly deeper into it as a software developer my enthusiasm for it has cooled down significantly. It's still great that we got a mainstream open ISA, but now I view it as a Linux of the hardware world, i.e. a great achievement, with a big number of questionable choices baked in, which unfortunately…

What choices? The main thing that comes to mind is lack of exceptions on integer overflow but you are unlikely meaning this.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#127

Post by adgjlsfhk1 » Mon, Sep 08, 2025, 9:58 PM UTC

fanf2 wrote: post #70

torginus wrote: post #18

Earlier quoted context omitted.

I remember reading this Jim Keller interview: https://web.archive.org/web/20210622080634/https://www.anand... Basically the gist of it is that the difference between ARM/x86 mostly boils down to instruction decode, and: - Most instructions end up being simple load/store/conditional branch etc. on both architectures, where there's literally no difference in encoding efficiency - Variable length instruction has pretty…

Apple’s ARM cores have wider decode than x86 M1 - 8 wide M4 - 10 wide Zen 4 - 4 wide Zen 5 - 8 wide

pure decoder width isn't enough to tell you everything. X86 has some commonly used ridiculously compact instructions (e.g. lea) that would turn into 2-3 instructions on most other architectures.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#128

Post by nottorp » Mon, Sep 08, 2025, 10:00 PM UTC

shmerl wrote: post #110

nottorp wrote: post #16

Irrelevant. There are two entities allowed to make x86_64 chips (and that only because AMD won the 64 bit ISA competition, otherwise there'd be only Intel). They get to choose. The rest will use arm because that's all they have access to. Oh, and x86_64 will be as power efficient as arm when one of the two entities will stop competing on having larger numbers and actually worry about power management. Maybe provide a…

AMD do handle power consumption well, at least if you run in eco mode instead of pushing CPU to the limits. I always set eco mode on on modern Ryzens.

I have a Ryzen box that I temperature limited to 65 C indeed. That was about 100 W in my office with just the graphics integrated into the Ryzen.

However, next to it there's a M2 mac mini that uses all of 37 W when I'm playing Cyberpunk 2077 so...

> Both Intel and AMD provide runtime power control so this is tunable. The last ~10% of performance requires far more than 10% of the power.

Yes but the defaults are insane.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#129

Post by Rohansi » Mon, Sep 08, 2025, 10:06 PM UTC

kragen wrote: post #88

kccqzy wrote: post #79

Earlier quoted context omitted.

This is the flip side of Intel trying to drop AVX512 on their E cores in the 12th generation processors. It didn't work. It requires the OS to know which processes need AVX512 before they get run. And processes themselves use cpuid to determine the capability of processors and they don't expect it to change. So you basically must determine in advance which processes can be run on E cores and never migrate between cor…

What if the kernel handled unimplemented instruction faults by migrating the process to a core that does implement the instruction and restarting the faulting instruction?

Sounds great for performance.

Re: AMD claims Arm ISA doesn't offer efficiency advantage over x86

#130

Post by kimixa » Mon, Sep 08, 2025, 10:07 PM UTC

adgjlsfhk1 wrote: post #127

fanf2 wrote: post #70

Earlier quoted context omitted.

Apple’s ARM cores have wider decode than x86 M1 - 8 wide M4 - 10 wide Zen 4 - 4 wide Zen 5 - 8 wide

pure decoder width isn't enough to tell you everything. X86 has some commonly used ridiculously compact instructions (e.g. lea) that would turn into 2-3 instructions on most other architectures.

Also the op cache - if it hits that the decoder is completely skipped.